公开(公告)号：US20240105630A1

公开(公告)日：2024-03-28

申请号：US17936037

申请日：2022-09-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Ching Meng Fang ,  Hin Hwa Goh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/162 ,  H01L25/165 ,  H01L21/563 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/95001 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

公开(公告)号：US20170186660A1

公开(公告)日：2017-06-29

申请号：US15457736

申请日：2017-03-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： See Chian Lim ,  Teck Tiong Tan ,  Yung Kuan Hsiao ,  Ching Meng Fang ,  Yoke Hor Phua ,  Bartholomew Liao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/15 ,  H01L21/768 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/145 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/11

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

公开(公告)号：US20240379479A1

公开(公告)日：2024-11-14

申请号：US18315098

申请日：2023-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Ching Meng Fang ,  Hin Hwa Goh

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor device includes a plurality of electrical components. A first encapsulant is deposited over the plurality of electrical components to form a module. The module is disposed adjacent to a semiconductor die. A second encapsulant is deposited over the semiconductor die and module. A build-up interconnect structure is formed over the second encapsulant, module, and semiconductor die.