公开(公告)号：US10297556B2

公开(公告)日：2019-05-21

申请号：US15415686

申请日：2017-01-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

公开(公告)号：US20240105630A1

公开(公告)日：2024-03-28

申请号：US17936037

申请日：2022-09-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Ching Meng Fang ,  Hin Hwa Goh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/162 ,  H01L25/165 ,  H01L21/563 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/95001 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

公开(公告)号：US20240071885A1

公开(公告)日：2024-02-29

申请号：US17823827

申请日：2022-08-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Jian Zuo ,  Hin Hwa Goh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/3511

Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.

公开(公告)号：US10177010B2

公开(公告)日：2019-01-08

申请号：US15235008

申请日：2016-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

公开(公告)号：US20240096807A1

公开(公告)日：2024-03-21

申请号：US17933149

申请日：2022-09-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Hin Hwa Goh ,  Jian Zuo

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5383 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/16 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.

公开(公告)号：US20170133330A1

公开(公告)日：2017-05-11

申请号：US15415686

申请日：2017-01-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/19 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

公开(公告)号：US20250140730A1

公开(公告)日：2025-05-01

申请号：US18498494

申请日：2023-10-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  DanFeng Yang ,  Hin Hwa Goh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01Q1/22

Abstract: A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component can be a direct metal bonded semiconductor die or a flipchip semiconductor die. The first interconnect structure can be an interposer unit or a conductive pillar. A split antenna is disposed over the electrical component and first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and second antenna section. A second interconnect structure is formed over the electrical component and first interconnect structure. The second interconnect structure has one or more conductive layers and insulating layers. The first interconnect structure and second interconnect structure provide a conduction path between the electrical component and split antenna. An encapsulant is deposited around the electrical component and first interconnect structure.

公开(公告)号：US20240379479A1

公开(公告)日：2024-11-14

申请号：US18315098

申请日：2023-05-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Ching Meng Fang ,  Hin Hwa Goh

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

Abstract: A semiconductor device includes a plurality of electrical components. A first encapsulant is deposited over the plurality of electrical components to form a module. The module is disposed adjacent to a semiconductor die. A second encapsulant is deposited over the semiconductor die and module. A build-up interconnect structure is formed over the second encapsulant, module, and semiconductor die.

公开(公告)号：US10790158B2

公开(公告)日：2020-09-29

申请号：US16206108

申请日：2018-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

公开(公告)号：US20190109015A1

公开(公告)日：2019-04-11

申请号：US16206108

申请日：2018-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/13

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.