公开(公告)号：US20240071885A1

公开(公告)日：2024-02-29

申请号：US17823827

申请日：2022-08-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Jian Zuo ,  Hin Hwa Goh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/3511

Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.

公开(公告)号：US20250087545A1

公开(公告)日：2025-03-13

申请号：US18462612

申请日：2023-09-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kai Chong Chan ,  Linda Pei Ee Chua ,  Yung Kuan Hsiao ,  Beng Yee Teh’ ,  Jian Zuo ,  Yaojian Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device has a pre-molded discrete electrical component and a first encapsulant deposited over the pre-molded discrete electrical component. A first conductive layer is formed over the first encapsulant and pre-molded discrete electrical component. An electrical component is disposed over the first conductive layer. A second encapsulant is deposited over the electrical component and first conductive layer. A second conductive layer is formed over the second encapsulant. A conductive pillar is formed between the first conductive layer and second conductive layer through the second encapsulant. The pre-molded discrete electrical component has a discrete component and a third encapsulant deposited around the discrete component. The discrete component has an electrical terminal, a finish formed over the electrical terminal, and a third conductive layer formed over the finish. An interconnect structure formed on the electrical component is oriented toward the first conductive layer or the second conductive layer.

公开(公告)号：US20240395647A1

公开(公告)日：2024-11-28

申请号：US18323594

申请日：2023-05-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jian Zuo ,  Lee Sun Lim

IPC: H01L23/31 ,  B23K26/38 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device has a plurality of electrical components and an encapsulant deposited over the electrical components. A first saw street of the encapsulant separates a first electrical component from a second electrical component. A first channel is formed in a first surface of the encapsulant within the first saw street to reduce stress. A second channel is formed in a second surface of the encapsulant opposite the first surface and within the first saw street. A third channel is formed in the first surface of the encapsulant and within a second saw street of the encapsulant normal to the first saw street. An RDL is formed over the electrical components. The RDL has an insulating layer formed over the electrical component, and a conductive layer formed over the insulating layer. The insulating layer terminates prior to the first saw street.

公开(公告)号：US20250132291A1

公开(公告)日：2025-04-24

申请号：US18492047

申请日：2023-10-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DanFeng Yang ,  Yaojian Lin ,  Linda Pei Ee Chua ,  Kai Chong Chan ,  Jian Zuo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

公开(公告)号：US12107058B2

公开(公告)日：2024-10-01

申请号：US17445330

申请日：2021-08-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jian Zuo ,  Yaojian Lin

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/03011 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05569 ,  H01L2224/06515

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

公开(公告)号：US20240096807A1

公开(公告)日：2024-03-21

申请号：US17933149

申请日：2022-09-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Hin Hwa Goh ,  Jian Zuo

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5383 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/16 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.

公开(公告)号：US20230056780A1

公开(公告)日：2023-02-23

申请号：US17445330

申请日：2021-08-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jian Zuo ,  Yaojian Lin

IPC: H01L23/00

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.