公开(公告)号：US20190103369A1

公开(公告)日：2019-04-04

申请号：US16208253

申请日：2018-12-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Pascal FORNARA ,  Guilhem BOUTON ,  Mathieu LISART

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L23/58 ,  H01L21/8234

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US20220122910A1

公开(公告)日：2022-04-21

申请号：US17566437

申请日：2021-12-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François TAILLIET ,  Guilhem BOUTON

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US20190165105A1

公开(公告)日：2019-05-30

申请号：US16241762

申请日：2019-01-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L27/112 ,  H01L29/78 ,  H01L21/763 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20140291858A1

公开(公告)日：2014-10-02

申请号：US14221401

申请日：2014-03-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Guilhem BOUTON ,  Patrick Regnier

IPC: H01L21/033 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  G03F1/38 ,  G03F1/50 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/0603 ,  H01L2224/0812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

Abstract translation: 一种制造用于在金属化层的轨道之间形成导电接触焊盘的光刻掩模的方法和形成在半导体晶片上的集成电路的电活性区域的方法包括形成第一掩模区域，其包括用于形成接触焊盘的第一开口区域 。 第一开口区具有低于阈值的第一开度。 形成包括附加开口区域的第二掩模区域，其中掩模的总体开度大于或等于阈值。

公开(公告)号：US20200052073A1

公开(公告)日：2020-02-13

申请号：US16657409

申请日：2019-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20190027565A1

公开(公告)日：2019-01-24

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Guilhem BOUTON ,  Pascal FORNARA ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US20180323141A1

公开(公告)日：2018-11-08

申请号：US16033109

申请日：2018-07-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François TAILLIET ,  Guilhem BOUTON

IPC: H01L23/522 ,  H01L21/66 ,  H01L49/02 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L22/22 ,  H01L22/32 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/60

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.