公开(公告)号：US20170278841A1

公开(公告)日：2017-09-28

申请号：US15279050

申请日：2016-09-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Vincenzo Palumbo ,  Elisabetta Pizzi

IPC: H01L27/02 ,  H01L21/283 ,  H01L23/00 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0288 ,  H01L21/283 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/48 ,  H01L24/49 ,  H01L28/60 ,  H01L2224/481 ,  H01L2224/48463 ,  H01L2224/49107 ,  H04L25/026

Abstract: An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions.

公开(公告)号：US20180097055A1

公开(公告)日：2018-04-05

申请号：US15454096

申请日：2017-03-09

Applicant: STMicroelectronics S.r.l.

Inventor： Elisabetta Pizzi ,  Fabrizio Fausto Renzo Toia ,  Marco Marchesi ,  Vincenzo Palumbo

IPC: H01L49/02 ,  H01L23/64 ,  H01F27/28 ,  H01F27/245 ,  H01F41/04 ,  H01F41/02

Abstract: A dielectric structure extends over the substrate and a transformer is integrated in the dielectric structure. The transformed includes a first winding in the dielectric layer at a first height and a second winding in the dielectric layer at a second height greater than the first height. The first and second windings are magnetically coupleable to one another. A magnetic element is positioned in alignment with the first and second windings. In one implementation, the magnetic element underlies the first winding in a position between the substrate and the first winding. In another implementation, the magnetic element overlies the second winding.

公开(公告)号：US09935098B2

公开(公告)日：2018-04-03

申请号：US15279050

申请日：2016-09-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Vincenzo Palumbo ,  Elisabetta Pizzi

IPC: H01L21/02 ,  H01L27/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L21/283

CPC classification number: H01L27/0288 ,  H01L21/283 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/48 ,  H01L24/49 ,  H01L28/60 ,  H01L2224/481 ,  H01L2224/48463 ,  H01L2224/49107 ,  H04L25/026

Abstract: An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions.

公开(公告)号：US20170250253A1

公开(公告)日：2017-08-31

申请号：US15250638

申请日：2016-08-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabrizio Fausto Renzo Toia ,  Claudio Contiero ,  Elisabetta Pizzi ,  Simone Dario Mariani

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/3247 ,  H01L21/74 ,  H01L21/743 ,  H01L23/535 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/7802

Abstract: A semiconductor device comprising: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

公开(公告)号：US11887948B2

公开(公告)日：2024-01-30

申请号：US17391192

申请日：2021-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Simone Dario Mariani ,  Elisabetta Pizzi ,  Daria Doria

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/56 ,  H01L24/03 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0219 ,  H01L2224/02181 ,  H01L2224/03019 ,  H01L2224/0382 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05647

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

公开(公告)号：US10199370B2

公开(公告)日：2019-02-05

申请号：US15900041

申请日：2018-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Vincenzo Palumbo ,  Elisabetta Pizzi

IPC: H01L27/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L21/283 ,  H01L23/48 ,  H04L25/02

Abstract: A method of manufacturing an electronic device for providing galvanic isolation includes forming a dielectric layer on a semiconductor body and integrating, in the dielectric layer, a galvanic isolation module, the integrating including forming a first metal region at a first height of the dielectric layer. A second metal region is formed at a second height greater than the first height of the dielectric layer, the first and second metal regions being at least one of capacitively and magnetically coupleable together. Forming the second metal region includes etching selective portions of the dielectric layer to form at least one trench having a side wall coupled to a bottom wall through rounded surface portions, and filling each trench with metal material to form the second metal region having rounded edges.

公开(公告)号：US10062757B2

公开(公告)日：2018-08-28

申请号：US15250638

申请日：2016-08-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabrizio Fausto Renzo Toia ,  Claudio Contiero ,  Elisabetta Pizzi ,  Simone Dario Mariani

IPC: H01L23/58 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/324 ,  H01L23/535 ,  H01L21/74

CPC classification number: H01L29/1087 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/3247 ,  H01L21/74 ,  H01L21/743 ,  H01L23/535 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/7802

Abstract: A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

公开(公告)号：US20180190646A1

公开(公告)日：2018-07-05

申请号：US15900041

申请日：2018-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Vincenzo Palumbo ,  Elisabetta Pizzi

IPC: H01L27/02 ,  H01L23/522 ,  H01L21/283 ,  H01L21/768 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/283 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L28/60 ,  H01L2224/45144 ,  H01L2224/481 ,  H01L2224/48463 ,  H01L2224/49107 ,  H04L25/026 ,  H01L2924/00014

Abstract: A method of manufacturing an electronic device for providing galvanic isolation includes forming a dielectric layer on a semiconductor body and integrating, in the dielectric layer, a galvanic isolation module, the integrating including forming a first metal region at a first height of the dielectric layer. A second metal region is formed at a second height greater than the first height of the dielectric layer, the first and second metal regions being at least one of capacitively and magnetically coupleable together. Forming the second metal region includes etching selective portions of the dielectric layer to form at least one trench having a side wall coupled to a bottom wall through rounded surface portions, and filling each trench with metal material to form the second metal region having rounded edges.