公开(公告)号：US20220359566A1

公开(公告)日：2022-11-10

申请号：US17870037

申请日：2022-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09559111B2

公开(公告)日：2017-01-31

申请号：US14790969

申请日：2015-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US11871571B2

公开(公告)日：2024-01-09

申请号：US17517137

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US11387249B2

公开(公告)日：2022-07-12

申请号：US16708482

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L27/11575 ,  H01L23/498 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L23/522 ,  H01L27/11565

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US09899411B2

公开(公告)日：2018-02-20

申请号：US15414345

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L21/8247 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/10 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

公开(公告)号：US09716102B2

公开(公告)日：2017-07-25

申请号：US15070247

申请日：2016-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JinGyun Kim ,  Myoungbum Lee ,  Seungmok Shin

IPC: H01L27/115 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L23/5226 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.

公开(公告)号：US09466612B2

公开(公告)日：2016-10-11

申请号：US14985730

申请日：2015-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

公开(公告)号：US20160118400A1

公开(公告)日：2016-04-28

申请号：US14985730

申请日：2015-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

IPC: H01L27/115 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

公开(公告)号：US09257441B2

公开(公告)日：2016-02-09

申请号：US14082657

申请日：2013-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

公开(公告)号：US20240164103A1

公开(公告)日：2024-05-16

申请号：US18418720

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.