公开(公告)号：US20220384500A1

公开(公告)日：2022-12-01

申请号：US17668566

申请日：2022-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungjun KIM ,  Jin-Hong PARK ,  Sunghun LEE ,  Keun HEO

IPC: H01L27/146

Abstract: A photodetector includes a gate electrode extending in a first direction, a ferroelectric layer on the gate electrode and maintaining a state of polarization formed by a gate voltage applied to the gate electrode, a light absorbing layer on the ferroelectric layer and extending in a second direction intersecting the gate electrode, the light absorbing layer including a two-dimensional (2D) material of a layered structure, a source electrode on the ferroelectric layer and connected to a first end of the light absorbing layer, and a drain electrode on the ferroelectric layer and connected to the a second end of the light absorbing layer.

公开(公告)号：US20220271057A1

公开(公告)日：2022-08-25

申请号：US17666448

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong PARK ,  Jin-Hong PARK ,  Sungjoo LEE

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/78

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

公开(公告)号：US20240006190A1

公开(公告)日：2024-01-04

申请号：US18117864

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jin-Hong PARK ,  Hogeun AHN ,  BoReum LEE ,  Sunguk JANG ,  Jiwan KOO ,  Seunghwan SEO

IPC: H01L21/467 ,  H01L29/66 ,  H01L21/441

CPC classification number: H01L21/467 ,  H01L29/66969 ,  H01L21/441

Abstract: A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.

公开(公告)号：US20140111782A1

公开(公告)日：2014-04-24

申请号：US13942854

申请日：2013-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hong PARK ,  Jeong-Ho YEO ,  Joo-On PARK ,  Chang-Min PARK

IPC: G03F7/20

CPC classification number: G03F7/70916

Abstract: Provided are a lithography apparatus, a method for lithography and a stage system. The lithography apparatus includes a reticle stage having a reticle, at least one nozzle on at least one surface of the reticle stage and configured to allow shielding gas to flow to a surface of the reticle to form an air curtain, and a gas supply unit configured to supply the nozzle with the shielding gas.

Abstract translation: 提供了一种光刻设备，一种光刻方法和一个舞台系统。 光刻设备包括具有掩模版的标线片台，在标线片台的至少一个表面上的至少一个喷嘴，并且被配置为允许保护气体流到标线片的表面以形成气帘;以及气体供给单元， 以向喷嘴供应保护气体。

公开(公告)号：US20240079496A1

公开(公告)日：2024-03-07

申请号：US18307914

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilsu JUNG ,  Jin-Hong PARK ,  Keun HEO ,  Sungjun KIM

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/45 ,  H01L29/51 ,  H01L29/76 ,  H10K10/46 ,  H10K10/84

CPC classification number: H01L29/78391 ,  H01L29/267 ,  H01L29/45 ,  H01L29/516 ,  H01L29/7606 ,  H10K10/466 ,  H10K10/472 ,  H10K10/84

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

公开(公告)号：US20230245887A1

公开(公告)日：2023-08-03

申请号：US18093653

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong PARK ,  Jin-Hyuk KIM ,  Jin-Hong PARK ,  Sejin KYUNG

IPC: H01L21/02 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/02614 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02568 ,  H01L27/14616 ,  H01L27/1461 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/0673

Abstract: Disclosed are methods of forming PN junction structures, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated by the same. The method of forming a PN junction structure includes: forming on a substrate a first material layer that includes first transition metal atoms and first chalcogen atoms, loading the first material layer into a process chamber and supplying a gas of second chalcogen atoms, and forming a second material layer by substituting the second chalcogen atoms for the first chalcogen atoms on a selected portion of the first material layer. The first material layer has one of n-type conductivity and p-type conductivity. The second material layer has the other of the n-type conductivity and the p-type conductivity.

公开(公告)号：US20220093803A1

公开(公告)日：2022-03-24

申请号：US17338400

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilsu JUNG ,  Jin-Hong PARK ,  Keun HEO ,  Sungjun KIM

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/51 ,  H01L29/45 ,  H01L29/76 ,  H01L51/05 ,  H01L51/10

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.