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公开(公告)号：US20140146461A1
公开(公告)日：2014-05-29
申请号：US14087095
申请日：2013-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-young Choi , Joon-young Oh , Hee-youb Kang , Jung-hoon Kim , Won-hwa Lee , Jae-beom Byun , Jong-yun Yun
IPC: H05K7/20
CPC classification number: G06F1/187 , G06F1/203 , G11B2220/60 , G11C5/00 , G11C5/02 , G11C5/025 , H05K7/20445
Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.
Abstract translation: 辅助存储器件包括：衬底和被配置为容纳衬底的至少一部分的壳体。 基板具有上下相对的表面，并且包括其第一半导体器件安装在上表面上的第一区域和第二半导体器件安装在上表面上的第二区域。 壳体包括覆盖第一区域的基板的上表面的第一子壳体和第一半导体器件。 第一子壳体不延伸以在第二区域覆盖基板的上表面。
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公开(公告)号：US20170358564A1
公开(公告)日：2017-12-14
申请号：US15622394
申请日：2017-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-young Lee , Joon-young Oh , Sung-wook Hwang , Yeoung-jun Cho
CPC classification number: H01L25/18 , H01L23/3121 , H01L23/3128 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L2224/02381 , H01L2224/04042 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49105 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83191 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/1431 , H01L2924/1436 , H01L2924/1438 , H01L2924/1461 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579 , H01L2924/181 , H01L2924/19107 , H01L2924/37001 , H01L2924/00012 , H01L2224/29099 , H01L2224/45099
Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.
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公开(公告)号：US10204892B2
公开(公告)日：2019-02-12
申请号：US15622394
申请日：2017-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-young Lee , Joon-young Oh , Sung-wook Hwang , Yeoung-jun Cho
IPC: H01L23/00 , H01L23/31 , H01L25/18 , H01L25/065
Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.
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公开(公告)号：US09684345B2
公开(公告)日：2017-06-20
申请号：US14087095
申请日：2013-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-young Choi , Joon-young Oh , Hee-youb Kang , Jung-hoon Kim , Won-hwa Lee , Jae-beom Byun , Jong-yun Yun
CPC classification number: G06F1/187 , G06F1/203 , G11B2220/60 , G11C5/00 , G11C5/02 , G11C5/025 , H05K7/20445
Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.
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