公开(公告)号：US08922008B2

公开(公告)日：2014-12-30

申请号：US13834475

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Yun Myung ,  Yong-Hwan Kwon ,  Jong-Bo Shim ,  Moon-Gi Cho

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract translation: 凸块结构包括第一凸块和第二凸块。 第一凸块设置在基板的连接焊盘上。 第一凸起包括具有第一宽度的下部，具有小于第一宽度的第二宽度的中间部分，以及具有大于第二宽度的第三宽度的上部。 第二凸块设置在第一凸块的上部。

公开(公告)号：US08928150B2

公开(公告)日：2015-01-06

申请号：US13889338

申请日：2013-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Gi Cho ,  Sun-Hee Park ,  Hwan-Sik Lim ,  Yong-Hwan Kwon

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68381 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Abstract translation: 多芯片封装可以包括第一和第二半导体芯片，绝缘层结构和插头结构。 第一半导体芯片可以包括第一接合焊盘。 第二半导体芯片可以位于第一半导体芯片上。 第二半导体芯片可以包括第二接合焊盘。 绝缘层结构可以覆盖半导体芯片的侧表面和上表面的至少一部分。 插塞结构可以通过电镀工艺形成在绝缘层结构中。 插头结构可以布置成与半导体芯片的侧表面间隔开，以将第一焊盘和第二焊盘彼此电连接。 具有第三接合焊盘的第三半导体芯片可以位于第二半导体芯片上。 因此，不需要在插头之间形成微凸块的工序。

公开(公告)号：US09449918B2

公开(公告)日：2016-09-20

申请号：US14798474

申请日：2015-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Gi Cho ,  Eun-Chul Ahn ,  Sang-Young Kim ,  Joo-Weon Shin ,  Min-Ho Lee

IPC: H01L29/00 ,  H01L23/525 ,  H01L27/112 ,  H01L23/532 ,  G06F12/02

CPC classification number: H01L23/5256 ,  G06F12/0246 ,  H01L23/5329 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

公开(公告)号：US09123725B2

公开(公告)日：2015-09-01

申请号：US14088654

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Gi Cho ,  Eun-Chul Ahn ,  Sang-Young Kim ,  Joo-Weon Shin ,  Min-Ho Lee

IPC: H01L29/80 ,  H01L23/525 ,  G06F12/02

CPC classification number: H01L23/5256 ,  G06F12/0246 ,  H01L23/5329 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

Abstract translation: 半导体器件通过防止通过修复过程的熔断体被电化学迁移电连接而提高了可靠性。 半导体器件包括衬底，熔丝，其包括形成在衬底上相同电平处的第一熔丝图案和第二熔丝图案，第一熔丝图案和第二熔丝图案彼此间隔开第一宽度，使得间隙 在所述保险丝设置在所述第一熔丝图案和所述第二熔丝图案之间的第一位置处，以及形成在所述第一熔丝图案和所述第二熔丝图案上的第一绝缘层，所述第一绝缘层包括位于所述第一位置上方的开口，并且具有 第二宽度小于第一宽度。