Storage controller managing completion timing, and operating method thereof

    公开(公告)号:US12013796B2

    公开(公告)日:2024-06-18

    申请号:US17751798

    申请日:2022-05-24

    IPC分类号: G06F13/16 G06F13/28

    摘要: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

    Storage controller managing completion timing, and operating method thereof

    公开(公告)号:US11366770B2

    公开(公告)日:2022-06-21

    申请号:US16983471

    申请日:2020-08-03

    IPC分类号: G06F13/16 G06F13/28

    摘要: A method of operating a storage controller that communicates with a host including a submission queue and a completion queue is provided. The operating method includes receiving a submission queue doorbell from the host, fetching a first command including a latency from the submission queue of the host in response to the received submission queue doorbell, processing the fetched first command, and writing a first completion, which indicates that the first command is completely processed, into the completion queue of the host at a timing based on the latency.

    STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF

    公开(公告)号:US20220283962A1

    公开(公告)日:2022-09-08

    申请号:US17751798

    申请日:2022-05-24

    IPC分类号: G06F13/16 G06F13/28

    摘要: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.