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    Multi-Level Redundancy Code for Non-Volatile Memory Controller
    5.
    发明申请
    Multi-Level Redundancy Code for Non-Volatile Memory Controller 有权
    非易失性存储器控制器的多级冗余码

    公开(公告)号：US20150301933A1

    公开(公告)日：2015-10-22

    申请号：US14256268

    申请日：2014-04-18

    Applicant: SanDisk Technologies Inc.

    Inventor： Daniel Tuers ,  Abhijeet Manohar

    IPC: G06F12/02 ,  G06F11/10 ,  H03M13/05

    CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/1032 ,  H03M13/05 ,  H03M13/09 ,  H03M13/1102

    Abstract: In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set.

    Abstract translation: 在非易失性存储器系统的控制器电路中，数据由控制器的功能块之间的CRC（循环冗余码）保护：在将数据组从一个功能块（诸如主机接口）发送到另一个功能块（ 例如数据加密或ECC），生成并传送相应的CRC数据。 在第二个块中，数据集可以在其对数据进行操作之前用第二块的CRC进行检查。 这允许控制器早期检查内部传输错误，允许重新请求损坏的数据，例如当将该过程应用于数据写入操作时从主机发送。 在第二个数据块完成数据之后，可以生成一个新的CRC，以便在其下一个内部传输时保护数据。 这种安排对于转换数据集的功能块特别有用。

    Finding Read Disturbs on Non-Volatile Memories
    6.
    发明申请
    Finding Read Disturbs on Non-Volatile Memories 有权
    寻找非易失性记忆中的干扰

    公开(公告)号：US20150262714A1

    公开(公告)日：2015-09-17

    申请号：US14215924

    申请日：2014-03-17

    Applicant: SanDisk Technologies Inc.

    Inventor： Daniel Tuers ,  Yosief Ataklti ,  Abhijeet Manohar

    IPC: G11C29/50 ,  G11C16/10 ,  G06F11/10

    CPC classification number: G11C29/50004 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C11/5642 ,  G11C16/102 ,  G11C16/32 ,  G11C16/3422 ,  G11C16/349 ,  G11C2029/5004 ,  G11C2211/5644

    Abstract: In non-volatile memory devices, the accessing of data on word line can degrade the data quality on a neighboring word line, in what is called a read disturb. Techniques are presented for determining word lines likely to suffer read disturbs by use of a hash tree for tracking the number of reads. Read counters are maintained for memory units at a relatively coarse granularity, such as a die or block. When the counter for one of these units reaches a certain level, it is subdivided into sub-units, each with their own read counter, in a process that be repeated to determine frequently read word lines with a fine level of granularity while only using a relatively modest amount of RAM on the controller to store the counters.

    Abstract translation: 在非易失性存储器件中，字线上的数据访问可以降低相邻字线上的数据质量，即所谓的读干扰。 提出了用于确定可能受到读取干扰的字线的技术，通过使用散列树来跟踪读取次数。 读取计数器以比较粗糙的粒度保持存储器单元，例如管芯或块。 当这些单元之一的计数器达到一定水平时，它被细分为子单元，每个子单元具有自己的读取计数器，在重复的过程中，以精确的粒度等级来确定频繁读取的字线，同时仅使用 相对适度的RAM在控制器上存储计数器。

    INHERENT ADAPTIVE TRIMMING
    7.
    发明申请
    INHERENT ADAPTIVE TRIMMING 审中-公开
    自适应修剪

    公开(公告)号：US20160291883A1

    公开(公告)日：2016-10-06

    申请号：US14675261

    申请日：2015-03-31

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Abhijeet Manohar ,  Daniel Tuers ,  Sathyanarayanan Subramanian ,  Judah Gamliel Hahn

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

    Abstract translation: 存储器系统可以使用自适应调整来控制来自主机到/从存储器的吞吐量和流量。 可以基于来自主机的数据速率自适应地改变存储器的修整参数。 编程速度可能会减慢，以减少磨损并提高耐力。 特别地，用于将数据从数据缓冲器传送到存储器（例如NAND闪存）的数据速率可以与主机数据速率相匹配。 可以在预测主机总线中的空闲时间时触发该编程速度降低。

    Multi-level redundancy code for non-volatile memory controller
    8.
    发明授权
    Multi-level redundancy code for non-volatile memory controller 有权
    用于非易失性存储器控制器的多级冗余码

    公开(公告)号：US09384128B2

    公开(公告)日：2016-07-05

    申请号：US14256268

    申请日：2014-04-18

    Applicant: SanDisk Technologies Inc.

    Inventor： Daniel Tuers ,  Abhijeet Manohar

    IPC: G06F12/02 ,  H03M13/05 ,  G06F11/10

    CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/1032 ,  H03M13/05 ,  H03M13/09 ,  H03M13/1102

    Abstract: In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set.

    Abstract translation: 在非易失性存储器系统的控制器电路中，数据由控制器的功能块之间的CRC（循环冗余码）保护：在将数据组从一个功能块（诸如主机接口）发送到另一个功能块（ 例如数据加密或ECC），生成并传送相应的CRC数据。 在第二个块中，数据集可以在其对数据进行操作之前用第二块的CRC进行检查。 这允许控制器早期检查内部传输错误，允许重新请求损坏的数据，例如当将该过程应用于数据写入操作时从主机发送。 在第二个数据块完成数据之后，可以生成一个新的CRC，以便在其下一个内部传输时保护数据。 这种安排对于转换数据集的功能块特别有用。

    Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory
    9.
    发明申请
    Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory 有权
    减少非易失性存储器部分写入块中的读取干扰的技术

    公开(公告)号：US20160141046A1

    公开(公告)日：2016-05-19

    申请号：US14543660

    申请日：2014-11-17

    Applicant: SanDisk Technologies, Inc.

    Inventor： Anubhav Khandelwal ,  Dana Lee ,  Abhijeet Manohar ,  Henry Chin ,  Gautam Dusija ,  Daniel Tuers ,  Chris Avila ,  Cynthia Hsu

    IPC: G11C16/34 ,  G11C11/56

    CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418

    Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

    Abstract translation: 呈现技术以减少部分写入的NAND型非易失性存储器块的读取干扰量，这两者都用于当确定块中的最后写入字线以及数据读取时。 在这两种情况下，通常使用未被写入的未选择字线，或者在找到最后写入的字线的情况下，可能未被写入的低通读出电压被偏置。 这种读取的结果也可以应用于通过跳过不同数量的字线来找到最后写入的字的算法。 通过使用比标准读取更短的位线建立时间，也可以改善最后写入的页面确定中的性能。

    Adaptive Data Re-Compaction After Post-Write Read Verification Operations
    10.
    发明申请
    Adaptive Data Re-Compaction After Post-Write Read Verification Operations 有权
    后写入读取验证操作后的自适应数据重新压缩

    公开(公告)号：US20150154069A1

    公开(公告)日：2015-06-04

    申请号：US14095881

    申请日：2013-12-03

    Applicant: SanDisk Technologies Inc.

    Inventor： Daniel Tuers ,  Thomas Ta ,  Abhijeet Manohar

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1072

    Abstract: Approaches are presented for adaptively re-compacting data when errors are found during a post-write verify in a non-volatile memory system, such as flash NAND memory. In one example, user data along with corresponding parity data is written into a block of non-volatile memory. After writing in the user data, but prior to writing the corresponding parity data, the user data is checked. For any word lines that fail this post-write verify, the parity data for the block is adjusted to remove the contribution of any failed word lines before this modified parity data is written into the block. The data corresponding to the failed word lines can then be written elsewhere in the memory system.

    Abstract translation: 在非易失性存储器系统（例如闪存NAND存储器）中的写入后验证期间发现错误时，呈现用于自适应地重新压缩数据的方法。 在一个示例中，用户数据连同对应的奇偶校验数据被写入非易失性存储器的块中。 在写入用户数据之后，但在写入相应的奇偶校验数据之前，检查用户数据。 对于任何失败这个写入后验证的字线，调整块的奇偶校验数据以消除在修改的奇偶校验数据写入块之前任何故障字线的贡献。 然后可以将与故障字线相对应的数据写入存储器系统中的其他地方。

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