-
1.发明申请公开(公告)号：US20110037175A1
公开(公告)日：2011-02-17
申请号：US12540759
申请日：2009-08-13
申请人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Solomon
发明人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Solomon
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76838 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.
摘要翻译： 形成了亚光刻间距结构和光刻凸出结构之间的互连。 具有亚光刻间距的多条导线可以被光刻图案化并且沿着与多根导线的长度方向成小于45度的角度的切割。 或者，与均聚物混合的共聚物可以放置在凹陷区域中并自对准以形成在恒定宽度区域具有亚光刻间距的多条导线，以及在梯形区域处的相邻线之间的光刻尺寸。 或者，具有亚光刻间距的第一多个导线和具有光刻间距的第二多个导线可以形成在相同的水平或不同的位置。
-
2.发明授权公开(公告)号：US08247904B2
公开(公告)日：2012-08-21
申请号：US12540759
申请日：2009-08-13
申请人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Soloman
发明人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Soloman
IPC分类号： H01L23/48
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76838 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.
摘要翻译： 形成了亚光刻间距结构和光刻凸出结构之间的互连。 具有亚光刻间距的多条导线可以被光刻图案化并且沿着与多根导线的长度方向成小于45度的角度的切割。 或者，与均聚物混合的共聚物可以放置在凹陷区域中并自对准以形成在恒定宽度区域具有亚光刻间距的多条导线，以及在梯形区域处的相邻线之间的光刻尺寸。 或者，具有亚光刻间距的第一多个导线和具有光刻间距的第二多个导线可以形成在相同的水平或不同的位置。
-
公开(公告)号：US08263477B2
公开(公告)日：2012-09-11
申请号：US12684331
申请日：2010-01-08
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译： 制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。
-
公开(公告)号：US20110169051A1
公开(公告)日：2011-07-14
申请号：US12684331
申请日：2010-01-08
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译： 制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。
-
公开(公告)号：US20120298963A1
公开(公告)日：2012-11-29
申请号：US13571392
申请日：2012-08-10
IPC分类号： H01L29/772
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.
摘要翻译： 用于制造PiN异质结隧道场效应晶体管（TFET）的结构包括：硅晶片，其包括对准沟槽，p型硅锗（SiGe）区域和p型SiGe区域下方的氢注入区域，以及 所述对准沟槽将所述硅晶片分成上硅区域和下硅区域，其中所述上硅区域包括所述对准沟槽和所述p型SiGe区域; 以及位于对准沟槽和p型SiGe区域上方的第一氧化物层，其填充对准沟槽并且结合到位于处理晶片上的第二氧化物层; 其中所述对准沟槽被配置为将包括所述PiN异质结TFET的器件的布线电平对准到所述p型SiGe区域。
-
公开(公告)号：US09728619B2
公开(公告)日：2017-08-08
申请号：US13610266
申请日：2012-09-11
IPC分类号： H01L29/423 , B82Y10/00 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.
-
公开(公告)号：US08946680B2
公开(公告)日：2015-02-03
申请号：US13571657
申请日：2012-08-10
IPC分类号： H01L29/72 , H01L29/06 , B82Y10/00 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H01L29/739 , H01L29/78 , H01L29/40
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。
-
公开(公告)号：US08921825B2
公开(公告)日：2014-12-30
申请号：US13608089
申请日：2012-09-10
IPC分类号： H01L29/06 , H01L29/786 , H01L29/423 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
摘要翻译： 场效应晶体管器件包括纳米线，包括设置在纳米线上的栅极电介质层的栅极堆叠，设置在电介质层上的栅极导体层和衬底，以及包括设置在基板上的侧壁接触部分的有源区域， 栅极堆叠，侧壁接触部分与纳米线电接触。
-
公开(公告)号：US08901659B2
公开(公告)日：2014-12-02
申请号：US13369375
申请日：2012-02-09
IPC分类号： H01L29/66
CPC分类号： H01L21/02603 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02664 , H01L29/0669 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66818 , H01L29/775 , H01L29/78696
摘要： Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
摘要翻译： 提供了包括具有从器件的源极侧朝向器件的漏极侧变宽的锥形轮廓的至少一个半导体纳米线的非平面半导体器件，其具有减小的栅极到漏极耦合并因此减小栅极感应漏极隧穿电流。
-
公开(公告)号：US08680510B2
公开(公告)日：2014-03-25
申请号：US12824288
申请日：2010-06-28
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02521 , H01L21/02543 , H01L21/02603 , H01L21/02658 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/775 , H01L29/778 , H01L29/78681 , H01L29/78696
摘要： A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.
摘要翻译： 提供了形成半导体的方法，并且包括将衬垫和纳米线图案化到晶片上，所述纳米线基本上与衬垫侧壁垂直并且基本上平行于晶片表面并且外延生长在纳米线的外表面上， 半导体材料，其相对于纳米线的材料而晶格失配并且基本上没有缺陷。
-
-
-
-
-
-
-
-
-
搜索结果
124 条记录 (耗时 0.031 秒)
