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公开(公告)号：US09099185B2
公开(公告)日：2015-08-04
申请号：US14136708
申请日：2013-12-20
Applicant: Seagate Technology LLC
Inventor： YoungPil Kim , Rodney Virgil Bowman , Dadi Setiadi , Wei Tian
CPC classification number: G11C16/14 , G11C11/56 , G11C11/5628 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/3495 , G11C2211/5641
Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.
Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，存储器单元被提供有多个可用的编程状态以适应多级单元（MLC）编程。 控制电路使用单电平单元（SLC）编程将单个位逻辑值存储到存储器单元，以在第一和第二可用编程状态之间提供第一读取裕度。 控制电路随后使用虚拟多电平单元（VMLC）编程将单个位逻辑值存储到存储器单元，以在第一可用编程状态和第三可用编程状态之间提供较大的第二读取余量。
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公开(公告)号：US09123640B2
公开(公告)日：2015-09-01
申请号：US13892675
申请日：2013-05-13
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , YoungPil Kim , Rodney Virgil Bowman
CPC classification number: H01L27/2481 , H01L27/2472 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.
Abstract translation: 存储器件包括一叠层，包括具有连续电绝缘材料层的连续导电材料字线层的多个交替层。 多个通孔垂直延伸穿过堆叠层，并且垂直位线设置在每个通孔内。 开关材料层将垂直位线与层叠层隔开，从而形成RRAM单元阵列。
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公开(公告)号：US09105361B2
公开(公告)日：2015-08-11
申请号：US13665443
申请日：2012-10-31
Applicant: Seagate Technology LLC
Inventor： YoungPil Kim , Rodney Virgil Bowman
CPC classification number: G11C29/702 , G11C5/063 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C29/804
Abstract: A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.
Abstract translation: 用于各种固态存储器（例如但不限于闪速存储器）的容错控制线配置。 根据一些实施例，装置包括多个存储器单元和容错控制线。 控制线具有连接到多个存储单元中的每一个的细长的第一导电路径。 细长的第二导电路径以与第一导电路径平行的间隔开的关系设置。 多个导电支撑构件插入在第一和第二导电路径之间以支撑第一导电路径上方的第二导电路径。
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公开(公告)号：US20150213901A1
公开(公告)日：2015-07-30
申请号：US14679654
申请日：2015-04-06
Applicant: Seagate Technology LLC
Inventor： YoungPil Kim , Dadi Setiadi , Wei Tian , Antoine Khoueir , Rodney V. Bowman
CPC classification number: G11C16/14 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C13/0069 , G11C13/0097 , G11C16/16 , G11C2013/0073 , G11C2211/5646
Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.
Abstract translation: 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 在一些实施例中，装置包括存储器单元阵列和双极性电荷泵。 双极性电荷泵具有正极性电压源，其向电荷存储装置施加正电压以将所选择的存储单元编程为第一编程状态;以及负极性电压源，其向电荷存储装置施加负电压 将所选择的存储器单元编程到不同的第二编程状态。
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公开(公告)号：US20150011062A1
公开(公告)日：2015-01-08
申请号：US14264605
申请日：2014-04-29
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , YoungPil Kim , Rodney Virgil Bowman
IPC: H01L29/66 , H01L29/423 , H01L29/40
CPC classification number: H01L29/66825 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L29/401 , H01L29/42324 , H01L29/7889
Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.
Abstract translation: 存储器阵列，其包括具有通道的第一存储器单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间; 以及具有通道的第二存储单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间，其中所述第一存储器单元和所述第二存储器单元彼此平行地定位。
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Patent Agency Ranking
公开(公告)号：US20140332748A1
公开(公告)日：2014-11-13
申请号：US13892675
申请日：2013-05-13
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , YoungPil Kim , Rodney Virgil Bowman
CPC classification number: H01L27/2481 , H01L27/2472 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.
Abstract translation: 存储器件包括一叠层，包括具有连续电绝缘材料层的连续导电材料字线层的多个交替层。 多个通孔垂直延伸穿过堆叠层，并且垂直位线设置在每个通孔内。 开关材料层将垂直位线与层叠层隔开，从而形成RRAM单元阵列。
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公开(公告)号：US20140119123A1
公开(公告)日：2014-05-01
申请号：US13665443
申请日：2012-10-31
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： YoungPil Kim , Rodney Virgil Bowman
CPC classification number: G11C29/702 , G11C5/063 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C29/804
Abstract: A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.
Abstract translation: 用于各种固态存储器（例如但不限于闪速存储器）的容错控制线配置。 根据一些实施例，装置包括多个存储器单元和容错控制线。 控制线具有连接到多个存储单元中的每一个的细长的第一导电路径。 细长的第二导电路径以与第一导电路径平行的间隔开的关系设置。 多个导电支撑构件插入在第一和第二导电路径之间以支撑第一导电路径上方的第二导电路径。
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公开(公告)号：US09263142B2
公开(公告)日：2016-02-16
申请号：US14679654
申请日：2015-04-06
Applicant: Seagate Technology LLC
Inventor： YoungPil Kim , Dadi Setiadi , Wei Tian , Antoine Khoueir , Rodney V. Bowman
CPC classification number: G11C16/14 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C13/0069 , G11C13/0097 , G11C16/16 , G11C2013/0073 , G11C2211/5646
Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.
Abstract translation: 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 在一些实施例中，装置包括存储器单元阵列和双极性电荷泵。 双极性电荷泵具有正极性电压源，其向电荷存储装置施加正电压以将所选择的存储单元编程为第一编程状态;以及负极性电压源，其向电荷存储装置施加负电压 将所选择的存储器单元编程到不同的第二编程状态。
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公开(公告)号：US09231086B2
公开(公告)日：2016-01-05
申请号：US14264605
申请日：2014-04-29
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Antoine Khoueir , YoungPil Kim , Rodney Virgil Bowman
IPC: H01L27/115 , H01L29/66 , H01L29/788 , H01L29/40 , H01L29/423
CPC classification number: H01L29/66825 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L29/401 , H01L29/42324 , H01L29/7889
Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.
Abstract translation: 存储器阵列，其包括具有通道的第一存储器单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间; 以及具有通道的第二存储单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间，其中所述第一存储器单元和所述第二存储器单元彼此平行地定位。
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公开(公告)号：US20150179268A1
公开(公告)日：2015-06-25
申请号：US14136708
申请日：2013-12-20
Applicant: Seagate Technology LLC
Inventor： YoungPil Kim , Rodney Virgil Bowman , Dadi Setiadi , Wei Tian
CPC classification number: G11C16/14 , G11C11/56 , G11C11/5628 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/3495 , G11C2211/5641
Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.
Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，存储器单元被提供有多个可用的编程状态以适应多级单元（MLC）编程。 控制电路使用单电平单元（SLC）编程将单个位逻辑值存储到存储器单元，以在第一和第二可用编程状态之间提供第一读取裕度。 控制电路随后使用虚拟多电平单元（VMLC）编程将单个位逻辑值存储到存储器单元，以在第一可用编程状态和第三可用编程状态之间提供较大的第二读取余量。
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