公开(公告)号：US12132090B2

公开(公告)日：2024-10-29

申请号：US18371814

申请日：2023-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Shinpei Matsuda ,  Shunpei Yamazaki

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/788 ,  H10B41/70

CPC classification number: H01L29/42324 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7883 ,  H10B41/70

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US11777005B2

公开(公告)日：2023-10-03

申请号：US17324386

申请日：2021-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Shinpei Matsuda ,  Shunpei Yamazaki

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/06 ,  H01L29/775 ,  H10B41/70 ,  H01L21/28 ,  H01L29/778

CPC classification number: H01L29/42324 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/7883 ,  H01L29/78696 ,  H10B41/70

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US11923707B2

公开(公告)日：2024-03-05

申请号：US17293215

申请日：2019-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Takayuki Ikeda ,  Munehiro Kozuma ,  Takanori Matsuzaki ,  Akio Suzuki ,  Seiya Saito

IPC: H02J7/00

CPC classification number: H02J7/0029 ,  H02J7/00712

Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.

公开(公告)号：US11049946B2

公开(公告)日：2021-06-29

申请号：US16572673

申请日：2019-09-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Shinpei Matsuda ,  Shunpei Yamazaki

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/1156 ,  H01L29/788 ,  H01L21/28 ,  H01L29/778 ,  H01L29/06 ,  H01L29/775

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US10477192B2

公开(公告)日：2019-11-12

申请号：US15702170

申请日：2017-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akio Suzuki ,  Naoto Kusumoto

IPC: H04N13/31 ,  H04N13/156 ,  H04N13/351 ,  H01L27/32 ,  G02B27/22 ,  H04N13/32 ,  H01L29/786 ,  G02F1/1335 ,  G02F1/1368 ,  G02F1/137 ,  H01L27/12 ,  G02F1/1333

Abstract: A display system which enables a stereoscopic image to be perceived by the naked eye is provided. The display system includes a display panel which can display a first image, a second image, a third image, and a fourth image. The first image has a region overlapping with the third image. The second image has a region overlapping with the fourth image. The first image and the third image are perceived by one of the right and left eyes and the second image and the fourth image are perceived by the other of the right and left eyes, so that a composite image of the first to fourth images is stereoscopically perceivable.

公开(公告)号：US09761733B2

公开(公告)日：2017-09-12

申请号：US14953632

申请日：2015-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Haruyuki Baba ,  Akio Suzuki ,  Hiromi Sawai ,  Masahiko Hayakawa ,  Noritaka Ishihara ,  Masashi Oota

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/203

CPC classification number: H01L29/7869 ,  H01L21/02266 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/203 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.

公开(公告)号：US12205892B2

公开(公告)日：2025-01-21

申请号：US17297863

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Atsushi Miyaguchi ,  Shunpei Yamazaki

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L29/786

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate.

公开(公告)号：US20180077408A1

公开(公告)日：2018-03-15

申请号：US15702170

申请日：2017-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akio Suzuki ,  Naoto Kusumoto

IPC: H04N13/04 ,  H04N13/00 ,  H01L27/32

CPC classification number: H04N13/31 ,  G02B27/2214 ,  G02F1/13338 ,  G02F1/133514 ,  G02F1/133528 ,  G02F1/1368 ,  G02F1/137 ,  G02F2201/44 ,  G02F2203/02 ,  G02F2203/09 ,  H01L27/1225 ,  H01L27/323 ,  H01L27/3232 ,  H01L27/3262 ,  H01L27/3269 ,  H01L27/3272 ,  H01L29/786 ,  H01L29/7869 ,  H04N13/156 ,  H04N13/32 ,  H04N13/351 ,  H04N2213/001

Abstract: A display system which enables a stereoscopic image to be perceived by the naked eye is provided. The display system includes a display panel which can display a first image, a second image, a third image, and a fourth image. The first image has a region overlapping with the third image. The second image has a region overlapping with the fourth image. The first image and the third image are perceived by one of the right and left eyes and the second image and the fourth image are perceived by the other of the right and left eyes, so that a composite image of the first to fourth images is stereoscopically perceivable.

公开(公告)号：US12081171B2

公开(公告)日：2024-09-03

申请号：US17923653

申请日：2021-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto Yakubo ,  Shoki Miyata ,  Akio Suzuki ,  Takayuki Ikeda

IPC: H03D7/14 ,  H01L29/786

CPC classification number: H03D7/1458 ,  H01L29/78648 ,  H01L29/7869

Abstract: A novel semiconductor device is provided. The semiconductor device includes a mixer circuit and a bias circuit. The mixer circuit includes a voltage-to-current conversion portion, a current switch portion, and a current-to-voltage conversion portion. The bias circuit includes a bias supply portion and a first transistor. The voltage-to-current conversion portion includes a second transistor and a third transistor. The bias supply portion has a function of outputting a bias voltage to be supplied to a gate of the second transistor and a gate of the third transistor. One of a source and a drain of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor. The first transistor is turned off when the bias voltage is supplied, and the first transistor is turned on when the supply of the bias voltage is stopped.

公开(公告)号：US10483365B2

公开(公告)日：2019-11-19

申请号：US15251382

申请日：2016-08-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio Suzuki ,  Shinpei Matsuda ,  Shunpei Yamazaki

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/788 ,  H01L27/1156

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.