公开(公告)号：US06624466B2

公开(公告)日：2003-09-23

申请号：US10074972

申请日：2002-02-12

申请人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

发明人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

公开(公告)号：US6162584A

公开(公告)日：2000-12-19

申请号：US73948

申请日：1998-05-07

申请人： Sen-Fu Chen ,  Chih-Heng Shen

发明人： Sen-Fu Chen ,  Chih-Heng Shen

IPC分类号： G03F7/00 ,  H01L21/02 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/06

CPC分类号： H01L28/20 ,  G03F7/0035 ,  H01L21/32155 ,  H01L21/823456 ,  H01L27/0629

摘要： A method is provided for forming a plurality of structures with different resistance values in a single polysilicon film as follows. Form a polysilicon layer upon a substrate. Pattern the polysilicon to expose a portion thereof which is to be reduced in thickness. Partially etch through the polysilicon to produce a reduced thickness thereof while leaving the remainder of the polysilicon with the original thickness. Dope the polysilicon layer through the polysilicon with variable doping as a function of the reduced thickness and the original thickness of the polysilicon.

摘要翻译： 提供一种用于在单个多晶硅膜中形成具有不同电阻值的多个结构的方法，如下。 在基板上形成多晶硅层。 对多晶硅进行图案化以暴露其厚度减小的部分。 部分地通过多晶硅蚀刻以产生其厚度减小，同时留下具有原始厚度的剩余多晶硅。 通过具有可变掺杂的多晶硅掺杂多晶硅层作为多晶硅的厚度减小和原始厚度的函数。

公开(公告)号：US06627971B1

公开(公告)日：2003-09-30

申请号：US09654777

申请日：2000-09-05

申请人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

发明人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

IPC分类号： H01L2900

CPC分类号： H01L21/32137 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L28/40

摘要： A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

摘要翻译： 具有不同电阻值的多个结构的器件形成在衬底上。 在基板上形成多晶硅层。 在衬底上形成氧化硅层。 在氧化硅层上形成硬掩模层。 硬掩模层包括全厚度部分和较薄部分。 全厚部分下面的多晶硅层被轻掺杂形成高电阻区域。 在较薄部分之下，多晶硅层被重掺杂形成低电阻区域。 然而，尽管电阻的差异，但是高电阻区域和低电阻区域具有相同的厚度。

公开(公告)号：US6071826A

公开(公告)日：2000-06-06

申请号：US249259

申请日：1999-02-12

申请人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

发明人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

IPC分类号： H01L21/336 ,  H01L27/146 ,  H01L21/00

CPC分类号： H01L29/6659 ,  H01L27/14601 ,  H01L27/14683

摘要： A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

摘要翻译： 一种用于形成CMOS图像传感器间隔结构的方法。 在基板上形成多晶硅栅电极; 第一电介质的薄层沉积在栅电极和衬底的顶部的暴露表面上。 接下来，沉积第二层电介质，之后进行蚀刻以形成电极间隔物。 沉积的第二介电层用作蚀刻停止层并且防止对栅电极的间隔物之间​​的衬底表面的损坏。 一种替代方法是使用薄层层作为停止层，并且在这样做时，由白色像素问题引起的源/漏损坏。

公开(公告)号：US06380030B1

公开(公告)日：2002-04-30

申请号：US09298448

申请日：1999-04-23

申请人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

发明人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

摘要翻译： 公开了一种在浮动栅极的下边缘和分裂栅极闪存单元的控制栅极之间形成可靠的氮化硅间隔物的方法。 这通过形成具有垂直侧壁的浮动栅极，在包括垂直侧壁的浮动栅极之上形成高温氧化物层，随后是氮化硅层，离子注入氮化物层，然后选择性地蚀刻以形成稳定的氮化硅间隔物 定义明确的矩形。

公开(公告)号：US6143474A

公开(公告)日：2000-11-07

申请号：US73950

申请日：1998-05-07

申请人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

发明人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  G03F7/00

CPC分类号： H01L21/32137 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L28/40

摘要： This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

摘要翻译： 该方法从形成在基板上的单个多晶硅膜形成具有不同电阻值的结构。 在多晶硅膜上形成硬掩模层。 在硬掩模层上形成光刻胶掩模。 通过光致抗蚀剂掩模部分地蚀刻硬掩模层以减少多晶硅的厚度，同时留下具有原始厚度的硬掩模层的其余部分。 在多晶硅膜中要设置低电阻的位置，厚度减小。 然后通过具有可变掺杂的硬掩模层作为硬掩模层的减小的厚度和原始厚度的函数来掺杂多晶硅层。

公开(公告)号：US06682659B1

公开(公告)日：2004-01-27

申请号：US09435669

申请日：1999-11-08

申请人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

发明人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

IPC分类号： H01L21311

CPC分类号： H01L21/76838 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76888

摘要： A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications. When directed towards forming patterned conductor layers, such as bond pads, the method optionally employs an inert plasma treatment of a patterned conductor layer followed by an aqueous ethanolamine treatment of the patterned conductor layer prior to a first plasma treatment of the patterned conductor layer.

摘要翻译： 一种钝化目标层的方法。 首先提供基板。 然后在基底上形成目标层，其中目标层容易受到与用于进一步处理基底的腐蚀性材料接触的腐蚀。 然后在使用采用包含氧化性气体的第一等离子体气体组合物的第一等离子体方法的同时，使用目标层形成被腐蚀的腐蚀敏感性的氧化目标层，以与用于进一步处理的腐蚀性材料接触 基质。 最后，在使用腐蚀性材料的同时，进一步处理基板。 当在微电子制造中形成接合焊盘时，该方法是有用的。 当指向形成图案化的导体层（例如接合焊盘）时，该方法可以在图案化的导体层的第一等离子体处理之前，任意地使用图案化导体层的惰性等离子体处理，然后进行图案化导体层的乙醇胺水溶液处理。

公开(公告)号：US06232172B1

公开(公告)日：2001-05-15

申请号：US09354673

申请日：1999-07-16

申请人： Sen-Fu Chen ,  Yuan-Ko Hwang ,  Huan-Wen Wang

发明人： Sen-Fu Chen ,  Yuan-Ko Hwang ,  Huan-Wen Wang

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  Y10S438/916

摘要： A method to prevent threshold shifts in MOS transistors due to auto-doping from heavily doped polysilicon layers. Isolation regions are provided in a semiconductor substrate separating active areas. A gate oxide layer is formed over the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A tungsten silicide layer is deposited overlying the polysilicon layer. The tungsten silicide layer and the first polysilicon layer are etched to form MOS gates and bottom electrodes for dual polysilicon capacitors. An interpoly dielectric layer is deposited overlying entire surface of the semiconductor substrate. A doped polysilicon layer is deposited overlying the interpoly dielectric layer. A sealing oxide layer is deposited overlying the doped polysilicon layer to prevent out-diffusion of impurity ions into the semiconductor substrate and thereby preventing auto-doping. The tungsten silicide layer is annealed. Ions are implanted to form drain and source regions. The fabrication of the integrated circuit device is completed.

摘要翻译： 一种防止由于重掺杂多晶硅层自掺杂导致的MOS晶体管阈值偏移的方法。 隔离区域设置在分离有源区域的半导体衬底中。 在半导体衬底的表面上形成栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 在多晶硅层上沉积硅化钨层。 蚀刻钨硅化物层和第一多晶硅层以形成用于双多晶硅电容器的MOS栅极和底部电极。 在半导体衬底的整个表面上沉积多层介电层。 掺杂多晶硅层沉积在层间绝缘层上。 沉积在掺杂多晶硅层上的密封氧化物层以防止杂质离子向半导体衬底的扩散，从而防止自掺杂。 硅化钨层退火。 植入离子以形成漏极和源极区域。 完成集成电路器件的制造。

公开(公告)号：US5763316A

公开(公告)日：1998-06-09

申请号：US800977

申请日：1997-02-19

申请人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang

发明人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76216 ,  H01L21/32

摘要： A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.

摘要翻译： 已经开发了用于在高密度集成电路中为微米和亚微米器件创建场氧化物隔离的工艺。 避免了在去除氮化硅掩模之后形成的衬底中的沟槽产生的结漏电问题。 本发明也将“鸟嘴”侵入小活动装置区域也被最小化。 这些目标通过在场氧化物氧化过程之前在隔离区域中去除氮化硅氧化掩模之后，在沟槽中添加多晶硅或非晶硅填充层来实现。

公开(公告)号：US6001538A

公开(公告)日：1999-12-14

申请号：US55442

申请日：1998-04-06

申请人： Sen-Fu Chen ,  Jie-Shing Wu ,  Fang-Cheng Chen ,  Tsung-Tser Lee

发明人： Sen-Fu Chen ,  Jie-Shing Wu ,  Fang-Cheng Chen ,  Tsung-Tser Lee

IPC分类号： H01L21/311 ,  H01L21/768 ,  G03F7/40 ,  B44C1/22 ,  C23F1/00 ,  G03F7/36 ,  C03L15/00

CPC分类号： H01L21/31116 ,  H01L21/76804

摘要： A method for etching bonding pad access openings in a passivation layer of an integrated circuit is described. The method utilizes a two step etching procedure wherein the first step etches isotropically through a major portion of the passivation layer under conditions which provide very high etch rate selectivities of the passivation material to the photoresist. These high selectivitities result in virtually no erosion of the photoresist while the greater part of the opening is etched. A second anisotropic etch step wherein the base of the access opening is defined faithfully replicates the dimensions of the mask pattern. This two step etch process permits the use of photoresist layers of moderate thickness as well as photoresist layers with thin regions, such as occur when the photoresist is deposited over the uneven surface topography typically found on unplanarized passivation layers. The minimal erosion of the photoresist during the isotropic etch step secures sufficient photoresist coverage in the thin regions to prevent penetration and attack of passivation over wiring lines in the uppermost wiring level of the integrated circuit.

摘要翻译： 描述了一种用于在集成电路的钝化层中蚀刻焊盘进入开口的方法。 该方法采用两步蚀刻方法，其中在向钝化材料提供非常高的钝化材料的蚀刻速率选择性的条件下，第一步骤各向同性蚀刻钝化层的主要部分。 这些高选择性导致光致抗蚀剂几乎没有腐蚀，同时蚀刻大部分开口。 第二各向异性蚀刻步骤，其中确定进入口的底部忠实地复制掩模图案的尺寸。 这种两步蚀刻工艺允许使用具有中等厚度的光致抗蚀剂层以及具有薄区域的光致抗蚀剂层，例如当光致抗蚀剂沉积在通常存在于非​​平面化钝化层上的不平坦表面形貌上时发生。 在各向同性蚀刻步骤期间光致抗蚀剂的最小侵蚀确保了薄区域中足够的光致抗蚀剂覆盖，以防止在集成电路的最上层布线层中的布线上的钝化穿透和侵蚀。