公开(公告)号：US20110255045A1

公开(公告)日：2011-10-20

申请号：US13084360

申请日：2011-04-11

申请人： Seung-Suk SON ,  Duk-Sung Kim ,  Man-Hong Na ,  Ji-Young Jeong ,  Jae-Hwa Park

发明人： Seung-Suk SON ,  Duk-Sung Kim ,  Man-Hong Na ,  Ji-Young Jeong ,  Jae-Hwa Park

IPC分类号： G02F1/1343 ,  H01L21/28 ,  H01L29/04

CPC分类号： G02F1/136286 ,  G02F1/136209 ,  G02F1/136213 ,  H01L27/1244

摘要： Provided are a display substrate, a liquid crystal display (LCD) including the display substrate, and a method of manufacturing the display substrate. The display substrate includes: an insulating substrate; a gate wiring formed on the insulating substrate and extending generally in a first direction; a data wiring which is insulated from the gate wiring, intersects the gate wiring, and which extends generally in a second direction; a pixel electrode formed in a pixel region defined by the gate wiring and the data wiring; and a storage wiring which is formed on the same layer as the gate wiring, is overlapped by the data wiring to be insulated from the data wiring, and which extends generally in the second direction, wherein each of the gate wiring and the storage wiring has a tapered surface oriented generally at an inclination angle of approximately 30 degrees or less with respect to the insulating substrate.

摘要翻译： 提供了一种显示基板，包括显示基板的液晶显示器（LCD）以及显示基板的制造方法。 显示基板包括：绝缘基板; 栅极布线，其形成在所述绝缘基板上并且大致沿第一方向延伸; 与栅极布线绝缘的数据布线与栅极布线相交，并且大致沿第二方向延伸; 形成在由栅极布线和数据布线限定的像素区域中的像素电极; 和与栅极配线相同的层上形成的存储布线与数据布线重叠，与数据布线绝缘，并且大致沿第二方向延伸，其中栅极布线和存储布线各自具有 通常以相对于绝缘基板大约30度或更小的倾斜角定向的锥形表面。

公开(公告)号：US08520183B2

公开(公告)日：2013-08-27

申请号：US13084360

申请日：2011-04-11

申请人： Seung-Suk Son ,  Duk-Sung Kim ,  Man-Hong Na ,  Ji-Young Jeong ,  Jae-Hwa Park

发明人： Seung-Suk Son ,  Duk-Sung Kim ,  Man-Hong Na ,  Ji-Young Jeong ,  Jae-Hwa Park

IPC分类号： G02F1/1333 ,  G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/136209 ,  G02F1/136213 ,  H01L27/1244

摘要： Provided are a display substrate, a liquid crystal display (LCD) including the display substrate, and a method of manufacturing the display substrate. The display substrate includes: an insulating substrate; a gate wiring formed on the insulating substrate and extending generally in a first direction; a data wiring which is insulated from the gate wiring, intersects the gate wiring, and which extends generally in a second direction; a pixel electrode formed in a pixel region defined by the gate wiring and the data wiring; and a storage wiring which is formed on the same layer as the gate wiring, is overlapped by the data wiring to be insulated from the data wiring, and which extends generally in the second direction, wherein each of the gate wiring and the storage wiring has a tapered surface oriented generally at an inclination angle of approximately 30 degrees or less with respect to the insulating substrate.

摘要翻译： 提供了一种显示基板，包括显示基板的液晶显示器（LCD）以及显示基板的制造方法。 显示基板包括：绝缘基板; 栅极布线，其形成在所述绝缘基板上并且大致沿第一方向延伸; 与栅极布线绝缘的数据布线与栅极布线相交，并且大致沿第二方向延伸; 形成在由栅极布线和数据布线限定的像素区域中的像素电极; 和与栅极配线相同的层上形成的存储布线与数据布线重叠，与数据布线绝缘，并且大致沿第二方向延伸，其中栅极布线和存储布线各自具有 通常以相对于绝缘基板大约30度或更小的倾斜角定向的锥形表面。

公开(公告)号：US20100029073A1

公开(公告)日：2010-02-04

申请号：US12468296

申请日：2009-05-19

申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

IPC分类号： H01L21/336 ,  H01L21/3105

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

公开(公告)号：US20090315091A1

公开(公告)日：2009-12-24

申请号：US12483761

申请日：2009-06-12

申请人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Jong-Min Baek ,  Jae-Hwa Park ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Hee-Sook Park

发明人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Jong-Min Baek ,  Jae-Hwa Park ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Hee-Sook Park

IPC分类号： H01L29/49 ,  H01L27/10

CPC分类号： H01L29/4933 ,  H01L21/28061 ,  H01L27/10873

摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer

摘要翻译： 栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

公开(公告)号：US20080093660A1

公开(公告)日：2008-04-24

申请号：US11653166

申请日：2007-01-12

申请人： Hee-Sook Park ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Woong-Hee Sohn ,  Jang-Hee Lee ,  Jae-Hwa Park

发明人： Hee-Sook Park ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Woong-Hee Sohn ,  Jang-Hee Lee ,  Jae-Hwa Park

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/40114 ,  H01L29/513

摘要： A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a second width smaller than the first width. The flash memory device further includes a sidewall spacer surrounding a side surface of the metal electrode to prevent oxidation of the metal electrode.

摘要翻译： 闪速存储器件包括半导体衬底，栅极绝缘层，其具有形成在半导体衬底上的第一宽度，以捕获从半导体衬底隧穿的载流子，以及栅极绝缘层上的金属电极，以接收隧道所需的电压。 金属电极的第二宽度小于第一宽度。 闪存器件还包括围绕金属电极的侧表面的侧壁间隔件，以防止金属电极的氧化。

公开(公告)号：US20060223249A1

公开(公告)日：2006-10-05

申请号：US11214680

申请日：2005-08-29

申请人： Jae-Hwa Park ,  Hee-Sook Park ,  Dae-Yong Kim ,  Jang-Hee Lee

发明人： Jae-Hwa Park ,  Hee-Sook Park ,  Dae-Yong Kim ,  Jang-Hee Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823828 ,  H01L21/823835 ,  H01L21/823842

摘要： In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.

摘要翻译： 在一个实施例中，半导体器件包括形成在半导体衬底上的半导体衬底和掺杂导电层。 在掺杂导电层上方形成扩散阻挡层。 扩散阻挡层包括非晶半导体材料。 在扩散阻挡层上形成欧姆接触层。 金属阻挡层形成在欧姆接触层上。 在金属阻挡层上形成金属层。

公开(公告)号：US20060110900A1

公开(公告)日：2006-05-25

申请号：US11283121

申请日：2005-11-18

申请人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Jang-Hee Lee ,  Jae-Hwa Park ,  Dong-Chan Lim ,  Byung-Hak Lee ,  Hee-Sook Park

发明人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Jang-Hee Lee ,  Jae-Hwa Park ,  Dong-Chan Lim ,  Byung-Hak Lee ,  Hee-Sook Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/28247 ,  H01L21/28044 ,  H01L29/4925

摘要： In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

摘要翻译： 在半导体器件中形成栅极的方法中，在衬底上形成第一预栅极结构。 第一预选栅极结构包括依次层叠在基板上的栅极氧化物层，多晶硅层图案和钨层图案。 在第一温度下使用氧自由基进行一次氧化处理，以调节栅极氧化物层的厚度以形成具有氧化钨的第二初步栅极结构。 使用含氢气体将钨氧化物还原成钨材料以形成栅极结构。 在栅极结构上可能不形成氧化钨，从而可以抑制晶须的产生。 因此，可能不会产生相邻布线之间的短路。

公开(公告)号：US20060014355A1

公开(公告)日：2006-01-19

申请号：US11233580

申请日：2005-09-23

申请人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Hee-Sook Park ,  Woong-Hee Sohn ,  Jong-Ryeol Yoo ,  Sun-Pil Yun ,  Jang-Hee Lee ,  Dong-Chan Lim

发明人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Hee-Sook Park ,  Woong-Hee Sohn ,  Jong-Ryeol Yoo ,  Sun-Pil Yun ,  Jang-Hee Lee ,  Dong-Chan Lim

IPC分类号： H01L21/20

CPC分类号： H01L21/76841 ,  H01L21/28061 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L29/4933 ,  H01L29/4941

摘要： Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.

公开(公告)号：US09847276B2

公开(公告)日：2017-12-19

申请号：US14463645

申请日：2014-08-19

申请人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

发明人： Pil-Kyu Kang ,  Byung Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Taeyeong Kim ,  Kwangjin Moon ,  Jae-Hwa Park ,  Sukchul Bang ,  Seongmin Son ,  Jin Ho An ,  Ho-Jin Lee ,  Jeonggi Jin

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

公开(公告)号：US09673133B2

公开(公告)日：2017-06-06

申请号：US14939394

申请日：2015-11-12

申请人： Jae-Hwa Park ,  Kwangjin Moon ,  Byung Lyul Park ,  Sukchul Bang

发明人： Jae-Hwa Park ,  Kwangjin Moon ,  Byung Lyul Park ,  Sukchul Bang

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.