公开(公告)号：US20090111219A1

公开(公告)日：2009-04-30

申请号：US12350065

申请日：2009-01-07

申请人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

发明人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

摘要翻译： 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US20050012225A1

公开(公告)日：2005-01-20

申请号：US10852732

申请日：2004-05-24

申请人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

发明人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

摘要翻译： 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US20120269010A1

公开(公告)日：2012-10-25

申请号：US13238435

申请日：2011-09-21

申请人： Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

发明人： Myung CHO ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

IPC分类号： G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.

摘要翻译： 存储器包括被配置为存储第一标志数据的至少一个第一标志单元，被配置为存储第二标志数据的至少一个第二标志单元，具有由第一标志单元的第一标志数据确定的电压电平的至少一个第一感测节点 至少一个第二感测具有由第二标志单元的第二标志数据确定的电压电平，选择电路被配置为响应于标志地址选择第一感测节点或第二感测节点; 以及确定电路，其具有内部节点，通过所述内部节点流过与所选择的感测节点的电压电平相对应的电流，并且被配置为通过使用一定数量的第一和第二标志数据来确定与所选择的感测节点对应的标志数据的逻辑值 电流流过内部节点。

公开(公告)号：US07953304B2

公开(公告)日：2011-05-31

申请号：US12500417

申请日：2009-07-09

申请人： Hyun-Man Jang ,  Do-Woon Kim ,  Ji-Hwan Kim

发明人： Hyun-Man Jang ,  Do-Woon Kim ,  Ji-Hwan Kim

IPC分类号： G02B6/00 ,  G02B6/26

CPC分类号： H01B12/02 ,  H01B7/32 ,  H02H1/0007 ,  H02H7/001 ,  Y02E40/641 ,  Y02E40/68

摘要： Disclosed is a superconducting power cable capable of quench detection, and a quench detection system using the superconducting power cable. The superconducting power cable capable of quench detection includes a former; a superconducting conductor layer composed of a superconducting wire and surrounding the former; a conductor layer quench detection coil interposed between the former and the superconducting conductor layer and surrounding the former; an insulating layer surrounding the superconducting conductor layer; and a shielding layer surrounding the insulating layer. This superconducting power cable may detect quench generated during its operation in real time.

公开(公告)号：US08351317B2

公开(公告)日：2013-01-08

申请号：US12946715

申请日：2010-11-15

申请人： Ji-Hwan Kim

发明人： Ji-Hwan Kim

IPC分类号： G11B7/00

CPC分类号： H01L21/268 ,  B23K26/0626 ,  B23K26/0643 ,  B23K26/0676 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02691 ,  H01S3/005 ,  H01S3/0085

摘要： Provided are a laser irradiation apparatus, an irradiation method using the same, and a method of crystallizing an amorphous silicon film using the same. Particularly, a laser irradiation apparatus which can reduce a deviation of an intensity of a laser beam, an irradiation method using the same, and a method of crystallizing an amorphous silicon film using the same, which can improve uniformity in crystallization into a polycrystalline silicon thin film, are provided.

摘要翻译： 提供了一种激光照射装置，使用该激光照射装置的照射方法和使用其的使非晶硅膜结晶的方法。 特别地，可以减少激光束的强度偏差的激光照射装置，使用该激光束的照射方法以及使用该激光照射装置的非晶硅膜的结晶方法，其可以提高结晶化为多晶硅薄片的均匀性 电影。

公开(公告)号：US20120269020A1

公开(公告)日：2012-10-25

申请号：US13232304

申请日：2011-09-14

申请人： Seong-Je PARK ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Myung Cho ,  Beom-Seok Hah

发明人： Seong-Je PARK ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Myung Cho ,  Beom-Seok Hah

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line.

摘要翻译： 用于操作非易失性存储器件的方法包括响应于程序命令和接收到的地址选择多个字线的字线，确定所选择的字线是否是字线中的字线，执行 响应于所述确定的结果对所述字线的第二字线组进行擦除操作，以及对所选择的字线执行编程操作。

公开(公告)号：US08289787B2

公开(公告)日：2012-10-16

申请号：US12974419

申请日：2010-12-21

申请人： Ji-Hwan Kim ,  Seong-Je Park

发明人： Ji-Hwan Kim ,  Seong-Je Park

IPC分类号： G11C7/00

CPC分类号： G11C7/04 ,  G11C16/10 ,  G11C16/30

摘要： A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region.

摘要翻译： 一种半导体存储器件，包括：温度检测器，被配置为响应于在包括多个存储器单元的芯区域中检测到的温度输出温度检测信号;以及编程电压发生器，其被配置为响应于所述温度而产生编程电压 检测信号并将产生的编程电压输出到核心区域。

公开(公告)号：US20050064848A1

公开(公告)日：2005-03-24

申请号：US10925236

申请日：2004-08-23

申请人： Ji-Hwan Kim ,  Byung-Jin Kim

发明人： Ji-Hwan Kim ,  Byung-Jin Kim

IPC分类号： H04M15/00 ,  H04B1/40 ,  H04M1/00 ,  H04M1/2745 ,  H04M1/56 ,  H04M1/57 ,  H04M15/28 ,  H04Q7/38 ,  H04W88/02

CPC分类号： H04M1/2745 ,  H04M1/56 ,  H04M1/57 ,  H04M2250/60

摘要： The present invention relates to a method of classifying and storing the call durations of a mobile communication terminal and, more particularly, to a method of classifying and storing call durations, which classifies call durations, call time categories, etc. related to calls with calling partners stored in the address book of the mobile communication terminal, so that the user can recognize his or her call pattern and control the amount of call traffic, thus efficiently utilizing the mobile communication terminal. When an incoming or outgoing call is started, a calling partner of the call is identified, and a timer is operated to count call duration. When the call is terminated, the timer is stopped, and the actual call duration with the calling partner is calculated, thus classifying the call duration. The classified call duration is stored in the information area according to the calling partner of the call.

摘要翻译： 本发明涉及一种对移动通信终端的呼叫持续时间进行分类和存储的方法，更具体地说，涉及一种对呼叫持续时间进行分类和存储的方法，其中呼叫持续时间，呼叫时间类别等通过主叫 存储在移动通信终端的地址簿中的合作伙伴，使得用户可以识别他或她的呼叫模式并控制呼叫业务量，从而有效地利用移动通信终端。 当呼入或呼出呼叫开始时，呼叫的呼叫伙伴被识别，并且操作定时器来计算呼叫持续时间。 当呼叫终止时，定时器停止，并且计算与呼叫伙伴的实际呼叫持续时间，从而对呼叫持续时间进行分类。 分类的呼叫持续时间根据呼叫的呼叫伙伴存储在信息区域中。

公开(公告)号：US08750048B2

公开(公告)日：2014-06-10

申请号：US13238435

申请日：2011-09-21

申请人： Myung Cho ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

发明人： Myung Cho ,  Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Beom-Seok Hah

IPC分类号： G11C16/34 ,  G11C16/28 ,  G11C16/06 ,  G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.

摘要翻译： 存储器包括被配置为存储第一标志数据的至少一个第一标志单元，被配置为存储第二标志数据的至少一个第二标志单元，具有由第一标志单元的第一标志数据确定的电压电平的至少一个第一感测节点 至少一个第二感测具有由第二标志单元的第二标志数据确定的电压电平，选择电路被配置为响应于标志地址选择第一感测节点或第二感测节点; 以及确定电路，其具有内部节点，通过所述内部节点流过与所选择的感测节点的电压电平相对应的电流，并且被配置为通过使用一定数量的第一和第二标志数据来确定与所选择的感测节点对应的标志数据的逻辑值 电流流过内部节点。

公开(公告)号：US08451665B2

公开(公告)日：2013-05-28

申请号：US13232304

申请日：2011-09-14

申请人： Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Myung Cho ,  Beom-Seok Hah

发明人： Seong-Je Park ,  Jung-Hwan Lee ,  Ji-Hwan Kim ,  Myung Cho ,  Beom-Seok Hah

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line.

摘要翻译： 用于操作非易失性存储器件的方法包括响应于程序命令和接收到的地址选择多个字线的字线，确定所选择的字线是否是字线中的字线，执行 响应于所述确定的结果对所述字线的第二字线组进行擦除操作，以及对所选择的字线执行编程操作。