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    Sidewall coverage for copper damascene filling
    1.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07514348B2

    公开(公告)日：2009-04-07

    申请号：US11860639

    申请日：2007-09-25

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Method of forming metal silicide
    2.
    发明授权
    Method of forming metal silicide 有权
    形成金属硅化物的方法

    公开(公告)号：US07205234B2

    公开(公告)日：2007-04-17

    申请号：US10772938

    申请日：2004-02-05

    申请人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    发明人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

    摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.

    摘要翻译： 已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。 该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。 首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的 通过原子层沉积工艺形成钛夹层。

    Sputtering process with temperature control for salicide application
    4.
    发明申请
    Sputtering process with temperature control for salicide application 审中-公开
    用于自杀剂应用的温度控制的溅射过程

    公开(公告)号：US20050092598A1

    公开(公告)日：2005-05-05

    申请号：US10702970

    申请日：2003-11-05

    申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

    发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

    IPC分类号： C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

    CPC分类号： H01L21/28518 ,  C23C14/16

    摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

    摘要翻译： 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

    Sidewall coverage for copper damascene filling
    5.
    发明授权
    Sidewall coverage for copper damascene filling 有权

    公开(公告)号：US06686280B1

    公开(公告)日：2004-02-03

    申请号：US09989802

    申请日：2001-11-20

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L2100

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    Method for forming incompletely landed via with attenuated contact resistance
    6.
    发明授权
    Method for forming incompletely landed via with attenuated contact resistance 有权
    通过减弱接触电阻形成不完全着陆通孔的方法

    公开(公告)号：US06531389B1

    公开(公告)日：2003-03-11

    申请号：US09467130

    申请日：1999-12-20

    申请人： Shau-Lin Shue ,  Mei-Yun Wang

    发明人： Shau-Lin Shue ,  Mei-Yun Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76838 ,  H01L21/76802 ,  Y10S438/958

    摘要： A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer. Incident to employing the purging of the via to form the purged via and the plasma passivating of the purged via to form the plasma passivated purged via, the conductor stud layer when formed into the plasma passivated purged via is formed with attenuated contact resistance with respect to the plasma passivated patterned conductor layer.

    摘要翻译： 一种通过电介质层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的导体层。 然后形成覆盖图案化导体层的电介质层。 然后通过电介质层形成通孔以访问图案化的导体层，其中通孔不完全地着落在图案化的导体层上。 然后在使用真空吹扫方法的同时吹扫通孔以形成清洗的通孔。 然后钝化净化的通孔并钝化暴露在清洗过的通孔内的图案化导体层，同时采用等离子体钝化方法形成等离子体钝化清洗的通孔和等离子体钝化的图案化导体层。 最后，然后形成通过导体柱层被钝化的等离子体钝化。 为了采用清洗通孔以形成清洗过的通孔和被清除通孔的等离子体钝化以形成等离子体钝化净化通孔的事件，当形成等离子体钝化净化过的通孔时，导体柱层形成相对于 等离子体钝化图案化导体层。

    Sidewall coverage for copper damascene filling
    8.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07282450B2

    公开(公告)日：2007-10-16

    申请号：US10733722

    申请日：2003-12-11

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。