公开(公告)号：US07211517B2

公开(公告)日：2007-05-01

申请号：US10476978

申请日：2002-09-05

申请人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

发明人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

IPC分类号： H01L21/311

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78636 ,  Y10S438/978

摘要： A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

摘要翻译： 本发明的半导体器件的制造方法包括：（a）在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14，第一导电层15和第一绝缘膜16; （b）选择性地去除半导体层，栅极绝缘膜，第一导电层和第一绝缘膜，以形成器件隔离沟槽; （c）在器件隔离[元件分离]沟槽中形成第二绝缘膜17，其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; （d）去除第二绝缘膜和第一绝缘膜的一部分，使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和（e）图案化第一导电层以形成栅电极。

公开(公告)号：US20050151172A1

公开(公告)日：2005-07-14

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。

公开(公告)号：US07485923B2

公开(公告)日：2009-02-03

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L29/772

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。

公开(公告)号：US06933569B2

公开(公告)日：2005-08-23

申请号：US10668349

申请日：2003-09-24

申请人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

发明人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

摘要翻译： 半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区 所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域 去除绝缘体上的半导体层。 完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

公开(公告)号：US20050250317A1

公开(公告)日：2005-11-10

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US07611934B2

公开(公告)日：2009-11-03

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US06975001B2

公开(公告)日：2005-12-13

申请号：US10163984

申请日：2002-06-06

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

摘要翻译： 半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域， 包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域 含有第二导电型杂质。

公开(公告)号：US07719043B2

公开(公告)日：2010-05-18

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US20070158700A1

公开(公告)日：2007-07-12

申请号：US10587845

申请日：2005-01-28

申请人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

发明人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7854 ,  H01L29/78609

摘要： A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is applied to the gate electrode.

摘要翻译： 一种场效应晶体管，包括：从基底的平面突出的半导体层; 设置在所述半导体层的相对侧表面上的栅电极; 介于栅电极和半导体层的侧表面之间的栅极绝缘膜; 以及引入第一导电型杂质的源极/漏极区域，其中半导体层在夹在源极/漏极区域之间的部分中具有沟道形成区域，并且在沟道形成区域a中的半导体层的上部 沟道杂质浓度调整区域，其中第二导电类型杂质的浓度高于半导体层的下部，并且在沟道杂质浓度调节区域中，在面向栅极绝缘体的侧表面部分中形成沟道 在对栅电极施加信号电压的工作状态下的沟道杂质浓度调整区域中的半导体层的膜。

公开(公告)号：US06306691B1

公开(公告)日：2001-10-23

申请号：US09470505

申请日：1999-12-22

申请人： Risho Koh

发明人： Risho Koh

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78648

摘要： In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

摘要翻译： 在体驱动的SOIMOSFET中，半导体层在绝缘体上方延伸，并且包括第一导电型高杂质浓度扩散层，低杂质浓度区和另一第一导电型高杂质浓度扩散层。 形成与低杂质浓度区域的顶部接触的第二导电型高杂质浓度半导体层。 底部电极形成在绝缘层内，使得底部电极被绝缘层包围。 底部电极位于低杂质浓度区域的下方，并由绝缘层与低杂质浓度区域分开。 重要的是，底部电极不会在第一导电性高杂质浓度区域之下延伸。