公开(公告)号：US07211517B2

公开(公告)日：2007-05-01

申请号：US10476978

申请日：2002-09-05

申请人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

发明人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

IPC分类号： H01L21/311

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78636 ,  Y10S438/978

摘要： A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

摘要翻译： 本发明的半导体器件的制造方法包括：（a）在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14，第一导电层15和第一绝缘膜16; （b）选择性地去除半导体层，栅极绝缘膜，第一导电层和第一绝缘膜，以形成器件隔离沟槽; （c）在器件隔离[元件分离]沟槽中形成第二绝缘膜17，其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; （d）去除第二绝缘膜和第一绝缘膜的一部分，使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和（e）图案化第一导电层以形成栅电极。

公开(公告)号：US20050151172A1

公开(公告)日：2005-07-14

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。

公开(公告)号：US07485923B2

公开(公告)日：2009-02-03

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L29/772

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。

公开(公告)号：US07611934B2

公开(公告)日：2009-11-03

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US06975001B2

公开(公告)日：2005-12-13

申请号：US10163984

申请日：2002-06-06

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

摘要翻译： 半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域， 包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域 含有第二导电型杂质。

公开(公告)号：US20050250317A1

公开(公告)日：2005-11-10

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US06933569B2

公开(公告)日：2005-08-23

申请号：US10668349

申请日：2003-09-24

申请人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

发明人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

摘要翻译： 半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区 所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域 去除绝缘体上的半导体层。 完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

公开(公告)号：US20090140322A1

公开(公告)日：2009-06-04

申请号：US11992961

申请日：2006-10-03

申请人： Takashi Nakagawa ,  Yukishige Saito

发明人： Takashi Nakagawa ,  Yukishige Saito

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L29/40114 ,  H01L29/7881

摘要： A first insulation film (silicon dioxide film) and a second insulation film (aluminum oxide film) are laminated on a surface of a silicon substrate in this order to form a gate insulation film. At least one element (aluminum) of elements, which constitutes the second insulation film but is different from elements commonly contained in the whole area of the first insulation film, is caused to be contained in a part of the first insulation film, whereby a charge trapping site region is formed in the first insulation film.

摘要翻译： 依次将第一绝缘膜（二氧化硅膜）和第二绝缘膜（氧化铝膜）层叠在硅基板的表面上，形成栅绝缘膜。 构成第二绝缘膜但与第一绝缘膜的整个区域中通常包含的元件不同的元件的至少一个元件（铝）被包含在第一绝缘膜的一部分中，由此， 捕获位置区域形成在第一绝缘膜中。

公开(公告)号：US09059402B2

公开(公告)日：2015-06-16

申请号：US13380092

申请日：2010-06-21

申请人： Munehiro Tada ,  Toshitsugu Sakamoto ,  Yuko Yabe ,  Yukishige Saito ,  Hiromitsu Hada

发明人： Munehiro Tada ,  Toshitsugu Sakamoto ,  Yuko Yabe ,  Yukishige Saito ,  Hiromitsu Hada

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/1233 ,  G11C13/0011 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

摘要： A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order.

摘要翻译： 所公开的电阻可变元件具有高可靠性，高密度化和良好的绝缘性能。 该装置提供一种电阻可变元件，其中包括主要包含铜的金属，阀金属的氧化物膜，含氧的离子传导层和第二电极的第一电极按此顺序层压。

公开(公告)号：US06916695B2

公开(公告)日：2005-07-12

申请号：US10188642

申请日：2002-07-03

申请人： Hitoshi Wakabayashi ,  Yukishige Saito

发明人： Hitoshi Wakabayashi ,  Yukishige Saito

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/915

摘要： One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

摘要翻译： 本发明的一个目的是在其栅极处抑制使用高熔点金属的氮化物的至少n沟道MISFET的阈值电压。 为了实现该目的，p沟道MISFET的栅电极109由形成在膜106上的氮化钛膜106和钨膜107构成，并且n沟道MISFET的栅极110a由 形成在膜106a上的氮化钛膜106a和钨膜107。 通过氮化钛膜106中的氮离子注入形成氮化钛膜106a以降低功函数。