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16 条记录 (耗时 0.02 秒)

    Spherical ferrite particles and ferrite resin composite for bonded magnetic core
    1.
    发明授权
    Spherical ferrite particles and ferrite resin composite for bonded magnetic core 失效
    用于粘结磁芯的球形铁氧体颗粒和铁氧体树脂复合材料

    公开(公告)号：US5198138A

    公开(公告)日：1993-03-30

    申请号：US773329

    申请日：1991-10-11

    申请人： Shigehisa Yamamoto ,  Masaru Kawabata

    发明人： Shigehisa Yamamoto ,  Masaru Kawabata

    IPC分类号： H01F1/26 ,  H01F1/36 ,  H01F1/37

    CPC分类号： H01F1/37 ,  H01F1/26 ,  H01F1/36

    摘要： Disclosed herein are ferrite particles for a bonded magnetic core comprising crystal grains of 5 to 15 .mu.m in average diameter, having an average particle diameter of 20 to 150 .mu.m and a magnetic permeability of not less than 24, and consisting essentially of 47 to 58 mol % of Fe.sub.2 O.sub.3, 10 to 30 mol % of nickel oxide, manganese oxide, nickel-managanese oxide (calculated as NiO, MnO or NiO.MnO) and 15 to 40 mol % of zinc oxide (calculated as ZnO).

    摘要翻译： 本发明公开了一种粘结磁芯的铁氧体颗粒，其包含平均粒径为5〜15μm，平均粒径为20〜150μm，磁导率不低于24的晶粒，基本上由47〜 58mol％的Fe 2 O 3，10〜30mol％的氧化镍，氧化锰，镍锰氧化物（以NiO，MnO或NiO.MnO计）和15〜40mol％的氧化锌（以ZnO计）。

    Semiconductor device testing apparatus and testing method thereof
    2.
    发明授权
    Semiconductor device testing apparatus and testing method thereof 失效
    半导体器件测试装置及其测试方法

    公开(公告)号：US6037794A

    公开(公告)日：2000-03-14

    申请号：US129699

    申请日：1998-08-05

    申请人： Shigehisa Yamamoto ,  Katsuya Shiga

    发明人： Shigehisa Yamamoto ,  Katsuya Shiga

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G01R31/02

    CPC分类号： G01R31/318505 ,  G01R31/2886 ,  G01R31/318511 ,  G01R31/2856

    摘要： An object is to obtain a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

    摘要翻译： 本发明的目的是获得能够提高探针和电源端子与信号端子之间的接触特性的半导体器件测试装置，同时确保测试晶片的产品利用效率。 提供在探针晶片（4）上的凸起（5）是与形成在测试晶片（1）上的各个芯片（2）中的焊盘（3）的位置成反射对称的相同位置的凸块（5），公共互连（6） 用于互连凸起（5）以提供相同的电源和信号;以及连接到公共互连（6）的端子（7），以从外部向公共互连（6）提供电源和信号。 当探针晶片（4）和测试晶片（1）放在一起时，凸块（5）与芯片（2）中的焊盘（3）接触。 公共互连（6）为芯片（2）中的焊盘（3）提供用于老化测试的电源和信号。

    Design aiding apparatus and method for designing a semiconductor device
    3.
    发明授权
    Design aiding apparatus and method for designing a semiconductor device 失效
    设计半导体器件的设计辅助设备和方法

    公开(公告)号：US06024478A

    公开(公告)日：2000-02-15

    申请号：US761901

    申请日：1996-12-09

    申请人： Shigehisa Yamamoto

    发明人： Shigehisa Yamamoto

    IPC分类号： G01R31/28 ,  G06F17/50 ,  G01R19/145

    CPC分类号： G06F17/5068

    摘要： An electric work station calculates an output load of a selected cell based on information from at least one of a design cell information library, a logic circuit information library and a layout information library. The work station further calculates a hot carrier dependent lifetime of a transistor in the cell by using the computed output load and information from a reliability information library, and verifies reliability of the cell by comparing the calculated lifetime with a reference value.

    摘要翻译： 电工站基于来自设计小区信息库，逻辑电路信息库和布局信息库中的至少一个的信息来计算所选小区的输出负载。 工作站通过使用计算出的输出负载和来自可靠性信息库的信息来进一步计算单元中晶体管的热载流子相关寿命，并通过将计算的寿命与参考值进行比较来验证单元的可靠性。

    Input protection circuit
    7.
    发明授权
    Input protection circuit 失效
    输入保护电路

    公开(公告)号：US5696398A

    公开(公告)日：1997-12-09

    申请号：US280972

    申请日：1994-07-27

    申请人： Shigehisa Yamamoto

    发明人： Shigehisa Yamamoto

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0255 ,  H01L27/0251

    摘要： An input protection circuit comprises an internal circuit and an input terminal, between which a pair of rectifying devices are interposed with polygonal diffusion regions of one and the other conduction types, which diffusion regions are formed longer along the width thereof orthogonal to the direction of current flow in the wiring than along the direction of current flow. The width of the contacts between said wiring and said diffusion regions is greater than the width of the wiring not having the contacts, thereby achieving a high electrostatic breakdown voltage.

    摘要翻译： 输入保护电路包括内部电路和输入端子，一对整流装置之间插入有一个和另一个导电类型的多边形扩散区域，该扩散区域沿着与电流方向正交的宽度形成较长 布线中的流动比沿电流方向流动。 所述布线和所述扩散区域之间的触点的宽度大于不具有触点的布线的宽度，从而实现高的静电击穿电压。

    Method of verifying semiconductor integrated circuit reliability and cell library database
    8.
    发明授权
    Method of verifying semiconductor integrated circuit reliability and cell library database 失效
    半导体集成电路可靠性和单元库数据库的验证方法

    公开(公告)号：US06470479B1

    公开(公告)日：2002-10-22

    申请号：US09548738

    申请日：2000-04-13

    申请人： Shigehisa Yamamoto

    发明人： Shigehisa Yamamoto

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022

    摘要： A method of verifying semiconductor integrated circuit reliability allows reliability verification of a large-scale semiconductor integrated circuit without any omission. Step S12 is to obtain a sum total (Cio) of inner-cell input/output load capacities in a selected cell on the basis of input and output load capacities registered in a cell library database (1A), and step S13 is to obtain wiring capacitance (Cic) between cells. In step S14, the sum total (Cio) of inner-cell input/output load capacities and the wiring capacitance (Cic) between cells are added to obtain output-terminal load capacity (COUT). On the basis of the output-terminal load capacity (COUT), a failure rate (FOUT) of an intercellular interconnect line is obtained in step S15, and a failure rate (Fcell) of inner-cell interconnect lines is obtained in step S16 from an equation registered in the cell library database (1A). Then, those failure rates (Fcell, FOUT) are added to obtain a total failure rate (Ftotal) in step S17.

    摘要翻译： 一种验证半导体集成电路可靠性的方法允许大规模半导体集成电路的可靠性验证而没有任何遗漏。 步骤S12是根据注册在单元库数据库（1A）中的输入和输出负载能力来获得所选单元中的内单元输入/输出负载能力的总和（Cio），步骤S13是获得布线 电容（Cic）。 在步骤S14中，添加内部单元输入输出负载能力的总和（Cio）和单元之间的布线电容（Cic）以获得输出端子负载能力（COUT）。 在输出端负载能力（COUT）的基础上，在步骤S15中获得细胞间互连线的故障率（FOUT），在步骤S16中获得内单元互连线的故障率（Fcell） 注册在细胞库数据库（1A）中的方程式。 然后，在步骤S17中，添加故障率（Fcell，FOUT）以获得总故障率（F total）。

    Burn-in method and burn-in device
    9.
    发明授权
    Burn-in method and burn-in device 失效
    老化方法和老化设备

    公开(公告)号：US06372528B1

    公开(公告)日：2002-04-16

    申请号：US09813801

    申请日：2001-03-22

    申请人： Shigehisa Yamamoto

    发明人： Shigehisa Yamamoto

    IPC分类号： G01R3126

    CPC分类号： G11C29/006 ,  G01R31/2855

    摘要： To provide a burn-in method and device capable of accelerating burn-in also in a peripheral circuit portion and a logic circuit portion as well as a memory cell array portion. A high temperature stress is applied to a wafer to be an evaluation object (Step SP11). Next, a low temperature stress and an electric stress are applied to the wafer (Step SP12). Then, it is decided whether a predetermined stress is applied to the wafer or not (Step SP13). If a result of the decision at the Step SP13 is “YES”, it is decided whether a defective portion is generated in each chip of the wafer or not (Step SP14). Referring to a chip decided to have a failure generated thereon as a result of the decision at the Step SP14, it is decided whether repair is executed for the defective portion or not (Step SP15). If a result of the decision at the Step SP15 is “YES”, the repair is executed for the defective portion (Step SP16).

    摘要翻译： 提供一种能够在外围电路部分和逻辑电路部分以及存储单元阵列部分中加速老化的老化方法和装置。 将作为评价对象的晶片施加高温应力（步骤SP11）。 接下来，向晶片施加低温应力和电应力（步骤SP12）。 然后，判定是否对晶片施加规定的应力（步骤SP13）。 如果步骤SP13的判断结果为“是”，则判定是否在晶片的每个芯片中产生缺陷部（步骤SP14）。 参考在步骤SP14中作出决定而决定其上产生故障的芯片，判定是否对缺陷部分执行修理（步骤SP15）。 如果步骤SP15的判定结果为“是”，则对缺陷部执行修理（步骤SP16）。