公开(公告)号：US20070170508A1

公开(公告)日：2007-07-26

申请号：US11729464

申请日：2007-03-29

申请人： Shigenobu Maeda ,  Young-Wug Kim

发明人： Shigenobu Maeda ,  Young-Wug Kim

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78645

摘要： In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

公开(公告)号：US20060022267A1

公开(公告)日：2006-02-02

申请号：US11024252

申请日：2004-12-28

申请人： Shigenobu Maeda ,  Young-Wug Kim

发明人： Shigenobu Maeda ,  Young-Wug Kim

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/44

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78645

摘要： In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

摘要翻译： 在制造半导体器件以提高半导体器件在硅化工艺中的结构稳定性的方法中，提供衬底以具有由隔离层限定的有源区。 在有源区和隔离层上形成蚀刻掩模以具有至少部分地暴露有源区的防硅图案。 在暴露的有源区上形成栅极结构。 栅极间隔物形成在位于硅化防止图案上的栅极结构的侧壁上。 使用栅极间隔物作为掩模在有源区上形成源/漏区，从而形成半导体器件。 由于在半导体器件的晶体管中可能不产生空隙，或者可能在硅化工艺中阻止晶体管的入侵，所以包括晶体管的半导体器件可能具有改进的可靠性和电特性。

公开(公告)号：US07217622B2

公开(公告)日：2007-05-15

申请号：US11024252

申请日：2004-12-28

申请人： Shigenobu Maeda ,  Young-Wug Kim

发明人： Shigenobu Maeda ,  Young-Wug Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78645

摘要： In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.

摘要翻译： 在制造半导体器件以提高半导体器件在硅化工艺中的结构稳定性的方法中，提供衬底以具有由隔离层限定的有源区。 在有源区和隔离层上形成蚀刻掩模以具有至少部分地暴露有源区的防硅图案。 在暴露的有源区上形成栅极结构。 栅极间隔物形成在位于硅化防止图案上的栅极结构的侧壁上。 使用栅极间隔物作为掩模在有源区上形成源/漏区，从而形成半导体器件。 由于在半导体器件的晶体管中可能不产生空隙，或者可能在硅化工艺中阻止晶体管的入侵，所以包括晶体管的半导体器件可能具有改进的可靠性和电特性。

公开(公告)号：US07105900B2

公开(公告)日：2006-09-12

申请号：US10388353

申请日：2003-03-13

申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。

公开(公告)号：US06498370B1

公开(公告)日：2002-12-24

申请号：US09695341

申请日：2000-10-24

申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

IPC分类号： H01L2701

CPC分类号： H01L29/78615

摘要： A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

摘要翻译： 提供绝缘体上硅（SOD集成电路和制造SOI集成电路的方法），在SOI衬底上形成至少一个隔离晶体管有源区和体线，晶体管有源区和体线被包围 通过与SOI衬底的埋置绝缘层接触的隔离层，将晶体管有源区的侧壁的一部分延伸到体线，由此，晶体管有源区域通过a 主体延伸部由主体绝缘层覆盖，在晶体管有源区域上形成绝缘栅极图案，栅极图案的一端与主体绝缘层重叠。

公开(公告)号：US06911397B2

公开(公告)日：2005-06-28

申请号：US10412522

申请日：2003-04-11

申请人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

发明人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

摘要翻译： 形成双镶嵌互连的方法采用低k介电有机聚合物作为绝缘层。 仅使用一个硬掩模层，使用与自对准间隔物的蚀刻速率不同的硬掩模层和蚀刻停止层来防止对绝缘层的灰化损伤。 此外，可以形成小于光刻工艺的分辨率极限的通孔。 结果，该过程被简化，并且不发生光致抗蚀剂尾部现象。

公开(公告)号：US06689648B2

公开(公告)日：2004-02-10

申请号：US10134798

申请日：2002-04-29

申请人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

IPC分类号： H01L2100

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

摘要翻译： SOI半导体器件及SOI半导体器件的制造方法本发明涉及一种SOI半导体器件的制造方法，其中由硅化物层形成的部分在隔离层中被横向限制在用于二极管或阱电阻器的扩散区域中的预定范围内。 以这种方式，可以固定硅化物层和扩散区域的侧面之间的距离长度，大于现有技术中可用的距离，从而最小化扩散区域侧面的功率泄漏。 在如此构造的SOI半导体器件中，用于二极管（或阱电阻器）的扩散区域由具有不同密度杂质层的双结结构中的间隔物构成（例如，P-或N-层分别围绕 P +或N +层），换句话说，仅在高密度的杂​​质层，P +或N +层上，或在单结结构中，其中间隔物限制在扩散区域中形成硅化物层的空间范围。

公开(公告)号：US20060246605A1

公开(公告)日：2006-11-02

申请号：US11428911

申请日：2006-07-06

申请人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

发明人： Mu-Kyoung Jung ,  Young-Wug Kim ,  Hee-Sung Kang

IPC分类号： H01L21/00

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a body extension region extending from an active region. A silicide layer may be formed or a ground line contact may be over-etched to form a conductive contact plug that may provide a current path between the body exterior regions and the source region of the driver transistor.

摘要翻译： 提供了当使用SOI时可以减少或消除浮体效应的SRAM单元及其制造方法。 SRAM的存取晶体管的浮体例如通过从有源区延伸的体延伸区域连接到驱动晶体管的源极区域。 可以形成硅化物层或接地线接触可能被过度蚀刻以形成可在主体外部区域和驱动晶体管的源极区域之间提供电流路径的导电接触插塞。

公开(公告)号：US07348636B2

公开(公告)日：2008-03-25

申请号：US11030245

申请日：2005-01-06

申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

摘要翻译： 在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在 半导体衬底。 然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

公开(公告)号：US20050116297A1

公开(公告)日：2005-06-02

申请号：US11030245

申请日：2005-01-06

申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

摘要翻译： 在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在 半导体衬底。 然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。