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    Multilayer interconnection structure including an alignment mark
    4.
    发明授权
    Multilayer interconnection structure including an alignment mark 失效
    多层互连结构包括对准标记

    公开(公告)号：US06677682B1

    公开(公告)日：2004-01-13

    申请号：US09620555

    申请日：2000-07-20

    申请人： Noriaki Fujiki ,  Shigeru Harada ,  Takashi Yamashita

    发明人： Noriaki Fujiki ,  Shigeru Harada ,  Takashi Yamashita

    IPC分类号： H01L23544

    CPC分类号： H01L23/544 ,  H01L21/76819 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interlayer insulating film (21) is formed on a substrate (1), and a polysilicon layer (10) is formed on the interlayer insulating film (21). An interlayer insulating film (22) is formed to cover the polysilicon layer (10), and a polysilicon layer (11) is formed on the interlayer insulating film (22). An interlayer insulating film (23) is formed to cover the interlayer insulating film (22). A hole (20M) for a mark to constitute an alignment mark or the like is formed from a surface (23S) of the interlayer insulating film (23) to the polysilicon layer (11). The hole (20M) for a mark is larger than a contact hole formed from the surface (23S) to the substrate (1) but is shallower than the contact hole. Consequently, a concave portion corresponding to the hole (20M) for a mark is formed, with difficulty, on a silicon oxide layer to be subjected to CMP polishing and then become an interlayer insulting film (4). Therefore, it is possible to prevent a slurry from remaining in the concave portion. Thus, it is possible to obtain a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattering of the slurry to be used for a CMP method.

    摘要翻译： 在基板（1）上形成层间绝缘膜（21），在层间绝缘膜（21）上形成多晶硅层（10）。 形成层间绝缘膜（22）以覆盖多晶硅层（10），并且在层间绝缘膜（22）上形成多晶硅层（11）。 形成层间绝缘膜（23）以覆盖层间绝缘膜（22）。 从层间绝缘膜（23）到多晶硅层（11）的表面（23S）形成用于构成对准标记等的标记的孔（20M）。 用于标记的孔（20M）大于从表面（23S）到基板（1）形成的接触孔，但是比接触孔浅。 因此，难以在氧化硅层上形成与用于标记的孔（20M）对应的凹部，进行CMP研磨后，成为层间绝缘膜（4）。 因此，可以防止浆料残留在凹部中。 因此，可以获得具有高可靠性的半导体器件，而没有由用于CMP方法的浆料的剩余或散射引起的诸如布线断开等的缺点。

    Semiconductor device having an improved lead connection structure and manufacturing method thereof
    10.
    发明授权
    Semiconductor device having an improved lead connection structure and manufacturing method thereof 失效
    具有改进的引线连接结构的半导体器件及其制造方法

    公开(公告)号：US06013951A

    公开(公告)日：2000-01-11

    申请号：US116242

    申请日：1998-07-16

    申请人： Tomohiro Ishida ,  Shigeru Harada ,  Takashi Yamashita

    发明人： Tomohiro Ishida ,  Shigeru Harada ,  Takashi Yamashita

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53271 ,  H01L23/5226 ,  H01L2924/0002

    摘要： A first polycide lead, which is formed on a silicon substrate, consists of a first doped polysilicon layer and a first tungsten silicide layer that is formed on the first doped polysilicon layer. An interlayer insulating film, which is formed on the silicon substrate, has an opening that reaches the first doped polysilicon layer. A second polycide lead, which is formed on the interlayer insulating film, consists of a second doped polysilicon layer that is connected to the first polycide lead in the opening and a second tungsten silicide layer that is formed on the second doped polysilicon layer. In the opening, the first and second doped polysilicon layers are in contact with each other at the side surfaces of the first polycide lead.

    摘要翻译： 形成在硅衬底上的第一多晶硅导线由形成在第一掺杂多晶硅层上的第一掺杂多晶硅层和第一钨硅化物层组成。 在硅衬底上形成的层间绝缘膜具有到达第一掺杂多晶硅层的开口。 形成在层间绝缘膜上的第二多孔化合物引线由连接到开口中的第一多晶硅引线的第二掺杂多晶硅层和形成在第二掺杂多晶硅层上的第二硅化钨层组成。 在开口中，第一和第二掺杂多晶硅层在第一多晶硅导线的侧表面处彼此接触。