公开(公告)号：US09203357B2

公开(公告)日：2015-12-01

申请号：US13433410

申请日：2012-03-29

申请人： Shinichi Miwa ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Naoki Kosaka

发明人： Shinichi Miwa ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Naoki Kosaka

IPC分类号： H01L27/085 ,  H01L23/66 ,  H03F1/56 ,  H01L27/02 ,  H01L27/06 ,  H03F3/195 ,  H03F3/21 ,  H03F3/24 ,  H01L23/64 ,  H01L21/8252

CPC分类号： H03F1/56 ,  H01L21/8252 ,  H01L23/647 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L2223/6655 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2203/21106 ,  H03F2203/21142 ,  H01L2224/45099 ,  H01L2924/00

摘要： A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

摘要翻译： 功率放大器包括：半导体衬底，包括晶体管单元，用于位于半导体衬底上的晶体管单元的漏极电极，位于半导体衬底上并连接到漏电极的漏极焊盘，位于半导体衬底中的离子注入电阻;以及 沿着漏极焊盘延伸和接触，位于半导体衬底上并与离子注入电阻接触的浮动电极以及位于半导体衬底之外的输出匹配电路。 功率放大器还包括将漏极焊盘连接到输出匹配电路的导线。

公开(公告)号：US08440538B2

公开(公告)日：2013-05-14

申请号：US13089343

申请日：2011-04-19

申请人： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

发明人： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

IPC分类号： H01L21/311 ,  H01L21/76

CPC分类号： H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W2. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W3. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.

摘要翻译： 在制造空中桥结构时，将第二抗蚀剂层施加在第一抗蚀剂层上。 抗蚀剂层被曝光和显影以具有预定的宽度W2。 应用第三抗蚀剂层。 第三抗蚀剂层也被曝光和显影以具有预定宽度W3。 将气桥形成材料层施加到由第一，第二和第三抗蚀剂层组成的层堆叠结构，形成空气桥。 去除抗蚀剂层，完成具有阶梯状横截面的空中桥梁的制造。

公开(公告)号：US20120094481A1

公开(公告)日：2012-04-19

申请号：US13089343

申请日：2011-04-19

申请人： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

发明人： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

IPC分类号： H01L21/768

CPC分类号： H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W2. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W3. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.

摘要翻译： 在制造空中桥结构时，将第二抗蚀剂层施加在第一抗蚀剂层上。 抗蚀剂层被曝光和显影以具有预定的宽度W2。 应用第三抗蚀剂层。 第三抗蚀剂层也被曝光和显影以具有预定宽度W3。 将气桥形成材料层施加到由第一，第二和第三抗蚀剂层组成的层堆叠结构，形成空气桥。 去除抗蚀剂层，完成具有阶梯状横截面的空中桥梁的制造。

公开(公告)号：US20110175686A1

公开(公告)日：2011-07-21

申请号：US12911764

申请日：2010-10-26

申请人： Shinsuke Watanabe ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Shinichi Miwa

发明人： Shinsuke Watanabe ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Shinichi Miwa

IPC分类号： H03B5/12

CPC分类号： H03B5/1847 ,  H03D2200/0086

摘要： A high frequency second harmonic oscillator includes a transistor, a first signal line connected at a first end to the base or gate of the transistor, a first shunt capacitor connected at a first end to a second end of the first signal line and at a second end to ground, a second signal line connected at a first end to the collector or drain of the transistor, a second shunt capacitor connected at a first end to a second end of the second signal line and at a second end to ground, and a high capacitance capacitor connected between the first signal line and the second signal line. The first signal line has a length equal to an odd integer multiple of one quarter of the wavelength of a fundamental signal, plus or minus one-sixteenth of the wavelength of the fundamental signal.

摘要翻译： 高频二次谐波振荡器包括晶体管，在第一端连接到晶体管的基极或栅极的第一信号线，在第一端连接到第一信号线的第二端的第一并联电容器， 在第一端连接到晶体管的集电极或漏极的第二信号线，在第一端连接到第二信号线的第二端并在第二端连接到地的第二并联电容器，以及 连接在第一信号线和第二信号线之间的高容量电容器。 第一信号线具有等于基本信号波长四分之一的奇整数倍的长度，加上或减去基波信号波长的十六分之一。

公开(公告)号：US20100052799A1

公开(公告)日：2010-03-04

申请号：US12473317

申请日：2009-05-28

申请人： Shinsuke Watanabe ,  Seiki Goto ,  Yoshihiro Tsukahara ,  Ko Kanaya

发明人： Shinsuke Watanabe ,  Seiki Goto ,  Yoshihiro Tsukahara ,  Ko Kanaya

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03B5/1847

摘要： A voltage controlled oscillator having low phase noise and including: a variable resonator including a varactor and a control voltage terminal; and an open-end stub connected in parallel to the variable resonator, the open-end stub having a length shorter than or equal to an odd multiple of one quarter of a wavelength of a harmonic signal plus one sixteenth of the wavelength of the harmonic signal, and longer than or equal to an odd multiple of one quarter of the wavelength of the harmonic signal minus one sixteenth of the wavelength of the harmonic signal. In this structure, a high Q value is realized for a fundamental wave frequency. Fluctuation in a control voltage due to a harmonic signal is controlled.

摘要翻译： 一种具有低相位噪声的压控振荡器，包括：包括变容二极管和控制电压端子的可变谐振器; 以及与可变谐振器并联连接的开路短截线，开路短截线长度短于或等于谐波信号的波长的四分之一加上谐波信号的波长的十六分之一的奇数倍 并且长于或等于谐波信号的四分之一波长的奇数倍减去谐波信号的波长的十六分之一。 在该结构中，对于基波频率实现高Q值。 控制由于谐波信号引起的控制电压的波动。

公开(公告)号：US08728866B2

公开(公告)日：2014-05-20

申请号：US13079055

申请日：2011-04-04

申请人： Ko Kanaya ,  Yoshihiro Tsukahara ,  Shinsuke Watanabe

发明人： Ko Kanaya ,  Yoshihiro Tsukahara ,  Shinsuke Watanabe

IPC分类号： H01L21/50 ,  H01L23/04

CPC分类号： H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/552 ,  H01L24/06 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole.

摘要翻译： 一种制造半导体器件的方法包括：在体晶片的第一主表面上形成电路图案和第一金属膜; 从主体晶片的第二主表面形成穿透体晶片的通孔并到达第一金属膜; 在体晶片的第二主表面的一部分上形成第二金属膜，在通孔的内壁上，以及暴露在通孔中的第一金属膜上; 在盖晶片的第一主表面上形成凹部; 在盖晶片的第一主表面上形成第三金属膜，包括在盖晶片的凹部内部; 其中所述凹部面向所述电路图案，并且所述第一金属膜与所述第三金属膜接触，将所述盖晶片接合到所述主体晶片; 并且沿着通孔对接合体晶片和盖晶片进行切割。

公开(公告)号：US20120025366A1

公开(公告)日：2012-02-02

申请号：US13079055

申请日：2011-04-04

申请人： Ko Kanaya ,  Yoshihiro Tsukahara ,  Shinsuke Watanabe

发明人： Ko Kanaya ,  Yoshihiro Tsukahara ,  Shinsuke Watanabe

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/552 ,  H01L24/06 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/16235 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole.

摘要翻译： 一种制造半导体器件的方法包括：在体晶片的第一主表面上形成电路图案和第一金属膜; 从主体晶片的第二主表面形成穿透体晶片的通孔并到达第一金属膜; 在体晶片的第二主表面的一部分上形成第二金属膜，在通孔的内壁上，以及暴露在通孔中的第一金属膜上; 在盖晶片的第一主表面上形成凹部; 在盖晶片的第一主表面上形成第三金属膜，包括在盖晶片的凹部内部; 其中所述凹部面向所述电路图案，并且所述第一金属膜与所述第三金属膜接触，将所述盖晶片接合到所述主体晶片; 并且沿着通孔对接合体晶片和盖晶片进行切割。

公开(公告)号：US07538719B2

公开(公告)日：2009-05-26

申请号：US11957542

申请日：2007-12-17

申请人： Ko Kanaya

发明人： Ko Kanaya

IPC分类号： G01S7/28 ,  G06G7/16

CPC分类号： G01S7/03 ,  G01S7/032 ,  H03D9/0633 ,  H05K1/0237

摘要： A mixer circuit includes: a rat race circuit including a ring-shaped transmission line with a first terminal, a second terminal, a third terminal, and a fourth terminal, the first to fourth terminals being disposed, in that order, clockwise along the transmission line and equally spaced λLO/4 from one another, except that the first terminal is spaced 3*λLO/4 from the fourth terminal, where λLO is the wavelength of the LO signal applied to the mixer circuit; an LO terminal connected to the first terminal; a first diode and a second diode connected in the same polarity to the second terminal and the fourth terminal, respectively; and an RF terminal and an IF terminal both connected to the third terminal. The frequency of the LO signal is one-half of the frequency of the RF signal applied to the mixer circuit.

摘要翻译： 混合器电路包括：大鼠赛跑电路，其包括具有第一端子，第二端子，第三端子和第四端子的环形传输线，所述第一至第四端子以该顺序沿着所述传输顺时针 线和等间隔的λLO/ 4，除了第一端子与第四端子间隔3 *λLO/ 4，其中λLO是施加到混频器电路的LO信号的波长; 连接到第一终端的LO终端; 分别以与第二端子和第四端子相同的极性连接的第一二极管和第二二极管; 以及连接到第三终端的RF终端和IF终端。 LO信号的频率是施加到混频器电路的RF信号的频率的一半。

公开(公告)号：US08548416B2

公开(公告)日：2013-10-01

申请号：US12527877

申请日：2007-11-15

申请人： Takuya Suzuki ,  Kenji Kawakami ,  Ko Kanaya ,  Yoichi Kitamura

发明人： Takuya Suzuki ,  Kenji Kawakami ,  Ko Kanaya ,  Yoichi Kitamura

IPC分类号： H04B1/28

CPC分类号： H03D7/02 ,  H01L23/66 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03D9/0633 ,  H01L2924/00

摘要： A two-terminal semiconductor device is formed on a semiconductor substrate. Two wiring patterns are respectively connected to terminals of the semiconductor device, and two electrode pads are respectively connected to the wiring patterns for connecting a signal input/output circuit formed on a separate substrate. Two parallel wiring patterns are respectively connected to the wiring patterns, and two reactance-circuit connection electrode pads are respectively connected to the parallel wiring patterns for electrically connecting a reactance circuit formed on the separate substrate separately from the signal input/output circuit.

摘要翻译： 在半导体衬底上形成二端子半导体器件。 两个布线图案分别连接到半导体器件的端子，并且两个电极焊盘分别连接到用于连接形成在单独基板上的信号输入/输出电路的布线图案。 两个平行布线图案分别连接到布线图案，并且两个电抗电路连接电极焊盘分别连接到并行布线图案，用于将形成在单独基板上的电抗电路与信号输入/输出电路分开地电连接。

公开(公告)号：US08229387B2

公开(公告)日：2012-07-24

申请号：US12526432

申请日：2007-04-25

申请人： Kenji Kawakami ,  Takuya Suzuki ,  Ko Kanaya ,  Yoichi Kitamura

发明人： Kenji Kawakami ,  Takuya Suzuki ,  Ko Kanaya ,  Yoichi Kitamura

IPC分类号： H04B1/26

CPC分类号： H03D9/0633 ,  H03D7/02

摘要： Provided is an even harmonic mixer which is reduced in cost and size. The even harmonic mixer includes: a transducer in which a conductor of a microstrip line is connected to a ground plane of a waveguide, for transducing an RF signal transmitted in a waveguide mode into a transmission mode of the microstrip line; an anti-parallel diode pair which is cascade-connected to a microstrip line side of the transducer, and formed on a semiconductor substrate; a branching circuit for branching an LO signal and an IF signal; an open-end stub which is disposed between the transducer and the anti-parallel diode pair, and has a line length of about ½ wavelength at an RF signal frequency; and an open-end stub which is disposed between the anti-parallel diode pair and the branching circuit, and has a line length of about ¼ wavelength at the RF signal frequency.

摘要翻译： 提供了一种降低成本和尺寸的均匀谐波混合器。 均匀谐波混频器包括：传感器，其中微带线的导体连接到波导的接地平面，用于将以波导模式传输的RF信号转换为微带线的传输模式; 反并联二极管对，其级联连接到换能器的微带线侧，并形成在半导体衬底上; 用于分支LO信号和IF信号的分支电路; 设置在换能器和反并联二极管对之间的开口短截线，并且在RF信号频率处具有大约1/2波长的线路长度; 以及设置在反并联二极管对和分支电路之间的开路短截线，并且在RF信号频率处具有约1/4波长的线路长度。