公开(公告)号：US20120094481A1

公开(公告)日：2012-04-19

申请号：US13089343

申请日：2011-04-19

Applicant: Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

Inventor： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

IPC: H01L21/768

CPC classification number: H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W2. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W3. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.

Abstract translation: 在制造空中桥结构时，将第二抗蚀剂层施加在第一抗蚀剂层上。 抗蚀剂层被曝光和显影以具有预定的宽度W2。 应用第三抗蚀剂层。 第三抗蚀剂层也被曝光和显影以具有预定宽度W3。 将气桥形成材料层施加到由第一，第二和第三抗蚀剂层组成的层堆叠结构，形成空气桥。 去除抗蚀剂层，完成具有阶梯状横截面的空中桥梁的制造。

公开(公告)号：US09111061B2

公开(公告)日：2015-08-18

申请号：US13726859

申请日：2012-12-26

Applicant: Hiroshi Otsuka ,  Toshiyuki Oishi ,  Yutaro Yamaguchi ,  Naoki Kosaka ,  Shinichi Miwa ,  Koji Yamanaka

Inventor： Hiroshi Otsuka ,  Toshiyuki Oishi ,  Yutaro Yamaguchi ,  Naoki Kosaka ,  Shinichi Miwa ,  Koji Yamanaka

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Abstract translation: 使用大信号等效电路模型的晶体管特性计算装置具有设置在漏极端子和源极端子之间的缓冲陷阱电路，使得包括电阻器和电容器的并联电路，二极管和包括电阻器和电阻器的另一并联电路 电容器依次串联连接。

公开(公告)号：US08471377B2

公开(公告)日：2013-06-25

申请号：US13091204

申请日：2011-04-21

Applicant: Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

Inventor： Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L24/80 ,  H01L21/6835 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/2003 ,  H01L29/7322 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/27831 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80123 ,  H01L2224/80129 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H05K1/14 ,  H05K2201/047 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract translation: 半导体电路衬底包括晶体管形成衬底和电路形成衬底。 晶体管形成衬底是GaN衬底并且具有位于其顶表面中的双极结晶体管（BJT）。 晶体管形成基板的底表面是平坦的并且具有接触区域。 电路形成用基板是化合物半导体以外的材料，不具有半导体活性元素。 电路形成基板具有平坦的顶表面，埋入并暴露在顶表面的接触区域和无源电路。 晶体管形成基板和电路形成基板直接接合在一起，而没有任何中间膜，例如绝缘膜。

公开(公告)号：US20140019096A1

公开(公告)日：2014-01-16

申请号：US13726859

申请日：2012-12-26

Applicant: Hiroshi OTSUKA ,  Toshiyuki OISHI ,  Yutaro YAMAGUCHI ,  Naoki KOSAKA ,  Shinichi MIWA ,  Koji YAMANAKA

Inventor： Hiroshi OTSUKA ,  Toshiyuki OISHI ,  Yutaro YAMAGUCHI ,  Naoki KOSAKA ,  Shinichi MIWA ,  Koji YAMANAKA

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036

Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Abstract translation: 使用大信号等效电路模型的晶体管特性计算装置具有设置在漏极端子和源极端子之间的缓冲陷阱电路，使得包括电阻器和电容器的并联电路，二极管和包括电阻器和电阻器的另一并联电路 电容器依次串联连接。

公开(公告)号：US20120032296A1

公开(公告)日：2012-02-09

申请号：US13091204

申请日：2011-04-21

Applicant: Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

Inventor： Naoki Kosaka ,  Hirotaka Amasuga ,  Kou Kanaya

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/80 ,  H01L21/6835 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/2003 ,  H01L29/7322 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/27831 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80123 ,  H01L2224/80129 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H05K1/14 ,  H05K2201/047 ,  H05K2201/10515 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract translation: 半导体电路基板包括晶体管形成基板和电路形成基板。 晶体管形成衬底是GaN衬底并且具有位于其顶表面中的双极结晶体管（BJT）。 晶体管形成基板的底表面是平坦的并且具有接触区域。 电路形成用基板是化合物半导体以外的材料，不具有半导体活性元素。 电路形成基板具有平坦的顶表面，埋入并暴露在顶表面的接触区域和无源电路。 晶体管形成基板和电路形成基板直接接合在一起，而没有任何中间膜，例如绝缘膜。

公开(公告)号：US09203357B2

公开(公告)日：2015-12-01

申请号：US13433410

申请日：2012-03-29

Applicant: Shinichi Miwa ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Naoki Kosaka

Inventor： Shinichi Miwa ,  Yoshihiro Tsukahara ,  Ko Kanaya ,  Naoki Kosaka

IPC: H01L27/085 ,  H01L23/66 ,  H03F1/56 ,  H01L27/02 ,  H01L27/06 ,  H03F3/195 ,  H03F3/21 ,  H03F3/24 ,  H01L23/64 ,  H01L21/8252

CPC classification number: H03F1/56 ,  H01L21/8252 ,  H01L23/647 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L2223/6655 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2203/21106 ,  H03F2203/21142 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

Abstract translation: 功率放大器包括：半导体衬底，包括晶体管单元，用于位于半导体衬底上的晶体管单元的漏极电极，位于半导体衬底上并连接到漏电极的漏极焊盘，位于半导体衬底中的离子注入电阻;以及 沿着漏极焊盘延伸和接触，位于半导体衬底上并与离子注入电阻接触的浮动电极以及位于半导体衬底之外的输出匹配电路。 功率放大器还包括将漏极焊盘连接到输出匹配电路的导线。

公开(公告)号：US20130032817A1

公开(公告)日：2013-02-07

申请号：US13433410

申请日：2012-03-29

Applicant: Shinichi MIWA ,  Yoshihiro TSUKAHARA ,  Ko KANAYA ,  Naoki KOSAKA

Inventor： Shinichi MIWA ,  Yoshihiro TSUKAHARA ,  Ko KANAYA ,  Naoki KOSAKA

IPC: H01L27/06

CPC classification number: H03F1/56 ,  H01L21/8252 ,  H01L23/647 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L2223/6655 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2203/21106 ,  H03F2203/21142 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

Abstract translation: 功率放大器包括：半导体衬底，包括晶体管单元，用于位于半导体衬底上的晶体管单元的漏极电极，位于半导体衬底上并连接到漏电极的漏极焊盘，位于半导体衬底中的离子注入电阻;以及 沿着漏极焊盘延伸和接触，位于半导体衬底上并与离子注入电阻接触的浮动电极以及位于半导体衬底之外的输出匹配电路。 功率放大器还包括将漏极焊盘连接到输出匹配电路的导线。

公开(公告)号：US08440538B2

公开(公告)日：2013-05-14

申请号：US13089343

申请日：2011-04-19

Applicant: Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

Inventor： Naoki Kosaka ,  Ko Kanaya ,  Yoshihiro Tsukahara

IPC: H01L21/311 ,  H01L21/76

CPC classification number: H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W2. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W3. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.

Abstract translation: 在制造空中桥结构时，将第二抗蚀剂层施加在第一抗蚀剂层上。 抗蚀剂层被曝光和显影以具有预定的宽度W2。 应用第三抗蚀剂层。 第三抗蚀剂层也被曝光和显影以具有预定宽度W3。 将气桥形成材料层施加到由第一，第二和第三抗蚀剂层组成的层堆叠结构，形成空气桥。 去除抗蚀剂层，完成具有阶梯状横截面的空中桥梁的制造。