公开(公告)号：US5357464A

公开(公告)日：1994-10-18

申请号：US22937

申请日：1993-02-26

申请人： Shuji Shukuri ,  Toru Koga ,  Shinichiro Kimura ,  Digh Hisamoto ,  Kazuhiko Sagara ,  Tokuo Kure ,  Eiji Takeda

发明人： Shuji Shukuri ,  Toru Koga ,  Shinichiro Kimura ,  Digh Hisamoto ,  Kazuhiko Sagara ,  Tokuo Kure ,  Eiji Takeda

IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/402 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/401 ,  H01L27/108

摘要： Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.

摘要翻译： 公开了具有自放大单元结构的半导体存储器，其使用（1）写入晶体管和（2）具有浮置栅极的读取晶体管作为每个存储单元的电荷存储节点，以及制造该存储单元的方法。 写入晶体管和读取晶体管彼此具有相反的导电类型; 例如，写入晶体管使用P沟道MOS晶体管，并且读取晶体管（具有浮置栅极）使用N沟道MOS晶体管。 读取晶体管的浮置栅极通过写入晶体管的源极 - 漏极连接到单个位线，读取晶体管的源极 - 漏极连接在单个位线和预定电位之间，并且栅电极 的写和读晶体管连接到单个字线。 至少读取晶体管可以形成在沟槽中，并且字线可以形成在沟槽中的写入晶体管和读取晶体管的上方。 还公开了一种操作存储单元的方法，其中在备用状态下施加到字线的电压在写入操作期间和在读取操作期间施加到字线的电压的中间。

公开(公告)号：US5200635A

公开(公告)日：1993-04-06

申请号：US686757

申请日：1991-04-17

申请人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

发明人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/456 ,  H01L2924/0002

摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

摘要翻译： 本发明涉及具有低电阻率布线结构的半导体器件。 直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。 这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。 在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。 上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面 和底层材料中的山谷。

公开(公告)号：US5177576A

公开(公告)日：1993-01-05

申请号：US695984

申请日：1991-05-06

申请人： Shin'ichiro Kimura ,  Tokuo Kure ,  Toru Kaga ,  Digh Hisamoto ,  Eiji Takeda

发明人： Shin'ichiro Kimura ,  Tokuo Kure ,  Toru Kaga ,  Digh Hisamoto ,  Eiji Takeda

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841

摘要： A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.

摘要翻译： 提供能够小型化的垂直半导体存储器件。 更具体地说，在动态随机存取存储器中提供具有沟槽电容器和垂直晶体管的存储单元，其适用于高密度集成。 这种布置的目的是提供一种能够小型化的垂直存储单元，用于Gbit级的超高密度集成DRAM。 该存储单元的特征在于，每个存储单元被氧化物膜覆盖，基板侧不存在杂质区域，形成沟道区域的区域是中空圆柱形单晶区域，杂质区域的连接为 源极 - 漏极区域和位线，并且电容器的电极通过自对准而形成，并且字线电极和栅电极之间的连接也通过自对准来进行。

公开(公告)号：US5270232A

公开(公告)日：1993-12-14

申请号：US943018

申请日：1992-09-10

申请人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/70

CPC分类号： H01L29/66606 ,  H01L21/28525 ,  H01L29/66621 ,  Y10S438/947

摘要： A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.

摘要翻译： 在基板上形成绝缘体膜和导体层的开口处形成非常薄的氧化膜，并且在开口的侧壁上形成含杂质的多晶硅。 通过非常薄的氧化膜从硅到衬底的杂质扩散导致扩散杂质的有效浓度降低，导致形成较浅的源/漏区。 此后，在由形成在开口的侧壁上的绝缘膜限定的区域中的基板表面上形成栅绝缘膜和栅电极。 小于开口的栅极电极，其尺寸对应于处理极限，并且较浅的源极/漏极区域提供小型化的MOSFET。

公开(公告)号：US08030668B2

公开(公告)日：2011-10-04

申请号：US11935904

申请日：2007-11-06

申请人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

发明人： Digh Hisamoto ,  Shinichi Saito ,  Shinichiro Kimura

IPC分类号： H01L27/15

CPC分类号： H01L27/15 ,  G02B6/13 ,  G02B6/43 ,  H01L33/02 ,  H01L33/34

摘要： A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

摘要翻译： 提供了高发光效率的发光二极管，并且包括通过现有技术的硅工艺在硅衬底上形成的等价于其的硅或锗等IV族半导体作为基底部件，以及其波导管的制造方法。 本发明的发光二极管包括用于注入电子的第一电极，用于注入孔的第二电极和与第一和第二电极电连接的发光部分，其中发光部分由单晶硅制成， 具有面向第一表面的第一表面和第二表面，其中相对于第一表面和第二表面的平面取向（100），使与第一表面和第二表面成直角交叉的发光部分变薄，并且其中 具有高折射率的材料设置在薄膜部分周围。

公开(公告)号：US07935597B2

公开(公告)日：2011-05-03

申请号：US12912609

申请日：2010-10-26

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US20090014775A1

公开(公告)日：2009-01-15

申请号：US12233670

申请日：2008-09-19

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/00

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20070210371A1

公开(公告)日：2007-09-13

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US20070183206A1

公开(公告)日：2007-08-09

申请号：US11727592

申请日：2007-03-27

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US08472258B2

公开(公告)日：2013-06-25

申请号：US13269425

申请日：2011-10-07

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。