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    Semiconductor device and driving method thereof
    4.
    发明授权
    Semiconductor device and driving method thereof 有权
    半导体装置及其驱动方法

    公开(公告)号：US08780629B2

    公开(公告)日：2014-07-15

    申请号：US13004942

    申请日：2011-01-12

    申请人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

    发明人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

    IPC分类号： G11C11/34 ,  G11C11/24 ,  G11C16/04 ,  H01L29/788

    CPC分类号： H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

    摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

    摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 有权
    半导体器件及其驱动方法

    公开(公告)号：US20110176355A1

    公开(公告)日：2011-07-21

    申请号：US13004942

    申请日：2011-01-12

    申请人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

    发明人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

    IPC分类号： G11C11/24

    CPC分类号： H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

    摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

    摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

    MEMORY DEVICE, MEMORY MODULE AND ELECTRONIC DEVICE
    8.
    发明申请
    MEMORY DEVICE, MEMORY MODULE AND ELECTRONIC DEVICE 有权
    存储器件，存储器模块和电子器件

    公开(公告)号：US20120161127A1

    公开(公告)日：2012-06-28

    申请号：US13331645

    申请日：2011-12-20

    申请人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

    发明人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

    IPC分类号： H01L29/78

    CPC分类号： H01L27/1156 ,  G11C11/404 ,  H01L27/1225

    摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

    摘要翻译： 第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。 第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜 并且在第二通道形成区域和第三栅电极之间。 第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110147737A1

    公开(公告)日：2011-06-23

    申请号：US12966611

    申请日：2010-12-13

    申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    IPC分类号： H01L29/12

    CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

    摘要翻译： 第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 并且设置包括第二源电极和第二漏电极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏极之一重叠的电极。 第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110128777A1

    公开(公告)日：2011-06-02

    申请号：US12952609

    申请日：2010-11-23

    申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    IPC分类号： G11C11/24 ,  H01L29/12 ,  G11C7/00

    CPC分类号： G11C11/405 ,  G11C16/0425 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

    摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

    摘要翻译： 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管形成在包括半导体材料的衬底上或衬底中。 第二晶体管包括氧化物半导体层。