公开(公告)号：US20180138906A9

公开(公告)日：2018-05-17

申请号：US14585201

申请日：2014-12-30

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H03K17/687 ,  H01H49/00

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US20170288034A1

公开(公告)日：2017-10-05

申请号：US15499487

申请日：2017-04-27

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088

CPC分类号： H01L29/42368 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/401 ,  H01L29/4236

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

公开(公告)号：US20160191048A1

公开(公告)日：2016-06-30

申请号：US14585201

申请日：2014-12-30

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H03K17/687 ,  H01H49/00

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

摘要翻译： 本发明公开了一种功率开关，其包括快速开关半导体功率器件和可控制的开关半导体功率器件，用于接通和断开通过其传输的电流。 慢开关半导体功率器件还包括用于增加慢开关半导体功率器件的器件鲁棒性的镇流电阻器。 在示例性实施例中，快速切换半导体功率器件包括快速开关金属氧化物半导体场效应晶体管（MOSFET），而慢开关半导体功率器件包括慢开关MOSFET，其中慢开关MOSFET还包括源极镇流电阻器。

公开(公告)号：US08963233B2

公开(公告)日：2015-02-24

申请号：US13436192

申请日：2012-03-30

申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

摘要翻译： 本发明公开了一种新的开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的半导体的第二表面附近的源极区域。 绝缘栅电极设置在第二表面的顶部，用于控制源极到漏极电流，并且源电极插入到绝缘栅电极中，用于基本上防止栅极电极和绝缘栅极之间的外延区域之间的电场的耦合 栅电极。 源极电极进一步覆盖并延伸在绝缘栅上，用于覆盖半导体的第二表面上的区域以接触源极区。外延层设置在漏极区之上并且具有不同掺杂剂浓度。 栅极通过具有取决于垂直功率器件的Vgsmax额定值的厚度的绝缘层与源电极绝缘。

公开(公告)号：US08946942B2

公开(公告)日：2015-02-03

申请号：US12074327

申请日：2008-03-03

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01H47/00 ,  H03K17/16 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US20140332882A1

公开(公告)日：2014-11-13

申请号：US13892312

申请日：2013-05-13

申请人： SiK K. Lui ,  Anup Bhalla

发明人： SiK K. Lui ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

公开(公告)号：US08643135B2

公开(公告)日：2014-02-04

申请号：US13134163

申请日：2011-05-31

申请人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/407 ,  H01L29/0661 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US20110204440A1

公开(公告)日：2011-08-25

申请号：US13066947

申请日：2011-04-28

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 构成活性单元的单元中的至少一个具有与沟槽栅极相邻设置的源极区域，该沟槽栅极电连接到栅极焊盘并围绕电池。 沟槽栅极还具有填充有栅极材料的底部屏蔽电极，栅极材料设置在沟槽栅极下方并与沟槽栅极绝缘。 构成由沟槽围绕的源极接触单元中的至少一个具有用作源极连接沟槽的部分的单元填充有栅极材料，用于电连接底部屏蔽电极和直接设置在源极连接沟槽顶部的源极金属 源连接沟槽。 半导体功率器件还包括设置在半导体功率器件的顶部上的绝缘保护层，其具有在源极区域的顶部上的多个源极开口和设置用于电连接到源极金属的源极连接沟槽和至少提供的栅极开口 用于将栅极焊盘电连接到沟槽栅极。

公开(公告)号：US20110042724A1

公开(公告)日：2011-02-24

申请号：US11634031

申请日：2009-04-20

申请人： Anup Bhalla ,  Sik K. Lui ,  Sung-Shan Tai

发明人： Anup Bhalla ,  Sik K. Lui ,  Sung-Shan Tai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

摘要翻译： 本发明公开了通过在半导体衬底的（110）晶体取向上形成沟槽的侧壁而制造的具有沟槽栅极的改进的MOSFET器件。 沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。 实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

公开(公告)号：US20100258897A1

公开(公告)日：2010-10-14

申请号：US12802790

申请日：2010-06-14

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66727 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/782 ,  H01L29/8725

摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。