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    Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode
    1.
    发明授权
    Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode 失效
    在具有自对准电容板电极的半导体衬底中制造单晶体管存储单元的TRENCH电容器的方法

    公开(公告)号：US5073515A

    公开(公告)日：1991-12-17

    申请号：US572262

    申请日：1990-08-27

    Applicant: Siegfried Roehl ,  Josef Mathuni

    Inventor： Siegfried Roehl ,  Josef Mathuni

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L27/10829

    Abstract: Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned cooperating capacitor electrode. In a one-transistor memory cell having a trench capacitor in a semiconductor substrate (1), a field oxide (3) that isolates different cells is exploited for a self-aligning process. After the formation of a first electrode and of a dielectrode (5) of the capacitor, a conductive layer (6) is applied surface-wide, the upper edge thereof being higher over the field oxide (3) than over the field-oxide-free locations of the substrate (1). The raised location is exposed in a re-etching process upon employment of a planarizing auxiliary layer (9), and a sub-layer (10, 10') is selectively applied thereon, either by local oxidation, selective or non-selective deposition. This sub-layer (10, 10') serves as a self-aligned mask for the structuring of the conductive layer (6) as a cooperating electrode of the trench capacitor.

    Abstract translation: 在具有自对准配合电容器电极的半导体衬底中制造单晶体管存储单元的沟槽电容器的方法。 在半导体衬底（1）中具有沟槽电容器的单晶体管存储单元中，利用隔离不同单元的场氧化物（3）进行自对准处理。 在电容器的第一电极和电介质（5）的形成之后，表面宽地施加导电层（6），其上边缘比场氧化物层（3）上面比场氧化物（3）高， 衬底（1）的自由位置。 在使用平面化辅助层（9）时，在再蚀刻工艺中暴露凸起位置，并且通过局部氧化，选择性或非选择性沉积选择性地在其上施加子层（10,10'）。 该子层（10,10'）用作用于构造作为沟槽电容器的配合电极的导电层（6）的自对准掩模。

    Method of structuring with metal oxide masks by reactive ion-beam etching
    2.
    发明授权
    Method of structuring with metal oxide masks by reactive ion-beam etching 失效
    通过反应离子束蚀刻用金属氧化物掩模构成的方法

    公开(公告)号：US4390394A

    公开(公告)日：1983-06-28

    申请号：US338605

    申请日：1982-01-11

    Applicant: Josef Mathuni ,  Karin Unger

    Inventor： Josef Mathuni ,  Karin Unger

    IPC: H01L21/302 ,  G03F7/09 ,  G03F7/40 ,  H01L21/033 ,  H01L21/3065 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

    CPC classification number: H01L21/0332 ,  G03F7/094 ,  G03F7/40 ,  Y10S438/949 ,  Y10S438/95

    Abstract: Very fine circuit structures in microelectronics are produced by first applying a thin metal oxide layer uniformly over an entire surface of a layer to be etched, then applying a resist layer uniformly over the entire metal oxide layer and structuring such oxide layer by ion-beam etching and, utilizing the structured oxide layer as a mask, performing a dry-etching with an ion beam of the metal layer lying thereunder so as to attain structures having very unfavorable resist height to etching depth ratios.

    Abstract translation: 通过首先在待蚀刻层的整个表面上均匀地施加薄的金属氧化物层，然后在整个金属氧化物层上均匀地施加抗蚀剂层并通过离子束蚀刻来构造这样的氧化物层来生产微电子中的非常精细的电路结构 并且利用结构化氧化物层作为掩模，利用其下面的金属层的离子束进行干蚀刻，以获得对蚀刻深度比非常不利的抗蚀剂高度的结构。

    Photomask, in particular alternating phase shift mask, with compensation structure
    3.
    发明授权
    Photomask, in particular alternating phase shift mask, with compensation structure 失效
    光掩模，特别是交替相移掩模，具有补偿结构

    公开(公告)号：US07063921B2

    公开(公告)日：2006-06-20

    申请号：US10667552

    申请日：2003-09-22

    Applicant: Wolfgang Dettman ,  Josef Mathuni ,  Oliver Fagerer ,  Bettina Schiessl ,  Stephen Rahn

    Inventor： Wolfgang Dettman ,  Josef Mathuni ,  Oliver Fagerer ,  Bettina Schiessl ,  Stephen Rahn

    IPC: G01F9/00 ,  G03C5/00

    CPC classification number: G03F1/34 ,  G03F1/30 ,  G03F1/36 ,  G03F1/40 ,  Y10T403/5773

    Abstract: The invention relates to a method for the production of masks, in particular for the production of alternating phase shift masks (1), or of chromeless phase shift masks or phase shift masks structured by quartz etching, respectively, as well as to a mask (1), in particular photomask, for the production of semiconductor devices, comprising at least one product field area (6a) and a compensation structure (5) positioned outside the product field area (6a), wherein the compensation structure (5) comprises at least one electroconductive region (8b) that is electrically connected with the product field area (6a).

    Abstract translation: 本发明涉及一种用于制造掩模的方法，特别是用于生产交替相移掩模（1）或由石英蚀刻构成的无铬相移掩模或相移掩模以及掩模（ 1），特别是光掩模，用于生产半导体器件，包括至少一个产品场区（6a）和位于产品场区（6a）外部的补偿结构（5），其中补偿结构（5） 包括与产品场区域（6a）电连接的至少一个导电区域（8b）。

    Method for damage etching the back side of a semiconductor disk having a protected front side
    4.
    发明授权
    Method for damage etching the back side of a semiconductor disk having a protected front side 失效
    用于损坏蚀刻具有受保护的正面​​的半导体盘的背面的方法

    公开(公告)号：US5693182A

    公开(公告)日：1997-12-02

    申请号：US604643

    申请日：1996-02-21

    Applicant: Josef Mathuni

    Inventor： Josef Mathuni

    IPC: C23F4/00 ,  H01L21/301 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78 ,  H01L21/00

    CPC classification number: H01L21/3086 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/78

    Abstract: A method for making large scale integrated circuits on a disklike semiconductor substrate includes grinding a disk thin enough to be able to be sawn apart into individual chips. A damage zone caused by the grinding on a back side of the wafer is removed by etching while protecting a front side of the wafer, prior to sawing. The etching is carried out in the form of a microwave or high-frequency-excited downstream plasma etching process using fluorine compounds in an etching gas.

    Abstract translation: 一种在盘状半导体衬底上制造大规模集成电路的方法包括：将足够薄的盘研磨成可分离成独立的芯片。 在切割之前，通过蚀刻除去晶片背侧的研磨引起的损伤区域，同时保护晶片的前侧。 蚀刻以蚀刻气体中的氟化合物的微波或高频激发下游等离子体蚀刻工艺的形式进行。

    Method for etching a semiconductor substrate and etching system
    7.
    发明授权
    Method for etching a semiconductor substrate and etching system 失效
    蚀刻半导体衬底和蚀刻系统的方法

    公开(公告)号：US5874366A

    公开(公告)日：1999-02-23

    申请号：US863371

    申请日：1997-05-27

    Applicant: Roland Sporer ,  Josef Mathuni ,  Alexander Gschwandtner

    Inventor： Roland Sporer ,  Josef Mathuni ,  Alexander Gschwandtner

    IPC: H01L21/306 ,  H01L21/00

    CPC classification number: H01L21/02052

    Abstract: The method and system of the invention allow etching even relatively thick layers on the rear side of a semiconductor substrate where the front side is resist-free. An etching solution is sprayed in fine droplets onto the rear side of the semiconductor substrate. The semiconductor substrate may thereby be heated to a temperature .ltoreq.100.degree. C.

    Abstract translation: 本发明的方法和系统允许在半导体衬底的背面没有抗蚀剂的情况下蚀刻甚至相当厚的层。 蚀刻溶液以细小的液滴喷射到半导体衬底的后侧。 因此可以将半导体衬底加热到​​100℃的温度。

    Device to generate excited/ionized particles in a plasma
    9.
    发明授权
    Device to generate excited/ionized particles in a plasma 有权
    在等离子体中产生激发/电离粒子的装置

    公开(公告)号：US06706141B1

    公开(公告)日：2004-03-16

    申请号：US09625200

    申请日：2000-07-21

    Applicant: Heinz Steinhardt ,  Alexander Gschwandtner ,  Josef Mathuni

    Inventor： Heinz Steinhardt ,  Alexander Gschwandtner ,  Josef Mathuni

    IPC: H05H100

    CPC classification number: H01J37/32229 ,  H01J37/32357 ,  H05H1/46

    Abstract: A device to generate excited and/or ionized particles in plasma with a generator to generate an electromagnetic wave and at least one plasma zone, in which the excited and/or ionized particles are formed by the electromagnetic wave. The plasma zone is formed in an interior chamber of a conductor for the electromagnetic wave.

    Abstract translation: 一种用发生器产生等离子体中的激发和/或电离粒子以产生电磁波和至少一个等离子体区域的装置，其中激发和/或离子化的颗粒由电磁波形成。 等离子体区域形成在用于电磁波的同轴导体的内部室中。

    Method for producing an alternating phase mask
    10.
    发明授权
    Method for producing an alternating phase mask 有权

    公开(公告)号：US06569772B2

    公开(公告)日：2003-05-27

    申请号：US10075540

    申请日：2002-02-14

    Applicant: Josef Mathuni ,  Jürgen Knobloch ,  Christoph Nölscher

    Inventor： Josef Mathuni ,  Jürgen Knobloch ,  Christoph Nölscher

    IPC: H01L21311

    CPC classification number: G03F1/30

    Abstract: A carrier has a surface with a mask layer thereon. An irradiation-sensitive layer on the mask layer is exposed and developed to form a first exposure structure. The first exposure structure is used as an etching mask while the mask layer is etched. The first exposure structure is subsequently removed. A second irradiation-sensitive layer is applied to the mask layer and the carrier. The second irradiation-sensitive layer is exposed with a first exposure dose and a second exposure dose. The second irradiation-sensitive layer is subsequently developed to form a second exposure structure with a first and second exposure structure thickness. The carrier is etched down to a first etching depth in the region of the first exposure structure thickness and down to a second etching depth in the region of the second exposure structure thickness. The first etching depth is larger than the second etching depth.

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