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    Package on package structure and fabrication method thereof
    2.
    发明授权
    Package on package structure and fabrication method thereof 有权
    封装结构及其制造方法

    公开(公告)号：US09362217B2

    公开(公告)日：2016-06-07

    申请号：US14290145

    申请日：2014-05-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Pang-Chun Lin ,  Wei-Ping Wang ,  Chun-Yuan Li ,  Shao-tzu Tang ,  Ying-Chou Tsai

    IPC: H01L21/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.

    Abstract translation: 公开了一种用于制造POP结构的方法。 首先，提供第一封装，其具有：介电层; 嵌入介电层中并从电介质层的上表面和下表面露出的堆叠电路层; 多个导电柱和设置在电介质层的上表面上并电连接到堆叠电路层的半导体芯片; 以及密封剂，其形成在所述电介质层的上表面上，用于封装所述半导体芯片和所述导电柱，并具有用于暴露所述导电柱的顶端的多个开口。 然后，第二包装被设置在密封剂上并电连接到导电柱。 导电柱的形成有助于减小密封剂的开口的深度，从而减少制造时间并提高生产效率和产率。

    PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
    4.
    发明申请
    PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF 有权
    包装结构及其制造方法

    公开(公告)号：US20150091150A1

    公开(公告)日：2015-04-02

    申请号：US14290145

    申请日：2014-05-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Pang-Chun Lin ,  Wei-Ping Wang ,  Chun-Yuan Li ,  Shao-tzu Tang ,  Ying-Chou Tsai

    IPC: H01L25/11 ,  H01L25/00

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.

    Abstract translation: 公开了一种用于制造POP结构的方法。 首先，提供第一封装，其具有：介电层; 嵌入介电层中并从电介质层的上表面和下表面露出的堆叠电路层; 多个导电柱和设置在电介质层的上表面上并电连接到堆叠电路层的半导体芯片; 以及密封剂，其形成在所述电介质层的上表面上，用于封装所述半导体芯片和所述导电柱，并具有用于暴露所述导电柱的顶端的多个开口。 然后，第二包装被设置在密封剂上并电连接到导电柱。 导电柱的形成有助于减小密封剂的开口的深度，从而减少制造时间并提高生产效率和产率。

    SEMICONDUCTOR PACKAGE STRUCTURE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构

    公开(公告)号：US20130200508A1

    公开(公告)日：2013-08-08

    申请号：US13834787

    申请日：2013-03-15

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC: H01L23/495

    CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

    Abstract translation: 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

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