公开(公告)号：US06627542B1

公开(公告)日：2003-09-30

申请号：US09604858

申请日：2000-06-27

申请人： Srinivas Gandikota ,  Rong Tao ,  Liang-Yuh Chen ,  Seshadri Ramaswami

发明人： Srinivas Gandikota ,  Rong Tao ,  Liang-Yuh Chen ,  Seshadri Ramaswami

IPC分类号： H01L2144

CPC分类号： H01L21/76868 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

摘要： A method and apparatus is provided for improving adherence of metal seed layers to barrier layers in electrochemical deposition techniques. The method includes depositing an adhesion layer continuously or semi-continuously without agglomeration onto a barrier layer prior to depositing a seed layer by controlling the substrate temperature, the chamber pressure, and/or the power delivered to a deposition chamber. Deposition of the adhesion layer prevents layer delamination which leads to agglomeration of the deposited layers and formation of voids in the high aspect ratio features.

摘要翻译： 提供了一种用于在电化学沉积技术中改善金属种子层对阻挡层的粘附性的方法和装置。 该方法包括通过控制衬底温度，室压力和/或输送到沉积室的功率沉积种子层之前将粘附层连续地或半连续地沉积在阻挡层上。 粘附层的沉积防止了层析层，导致沉积层的聚集和高纵横比特征形成空隙。

公开(公告)号：US06207222B1

公开(公告)日：2001-03-27

申请号：US09379696

申请日：1999-08-24

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： B05D512

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US6139697A

公开(公告)日：2000-10-31

申请号：US792292

申请日：1997-01-31

申请人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

发明人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  C23C14/34

CPC分类号： H01L21/76877

摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.

摘要翻译： 本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。 所得到的CVD / PVD ​​Cu层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。 本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

公开(公告)号：US5989623A

公开(公告)日：1999-11-23

申请号：US914521

申请日：1997-08-19

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  B05D5/12

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76807

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US06200433B1

公开(公告)日：2001-03-13

申请号：US09430998

申请日：1999-11-01

申请人： Peijun Ding ,  Rong Tao ,  Barry Chin ,  Dan Carl

发明人： Peijun Ding ,  Rong Tao ,  Barry Chin ,  Dan Carl

IPC分类号： C23C1442

CPC分类号： C23C14/046 ,  C23C14/358

摘要： The present invention generally provides a copper metallization method for depositing a conformal barrier layer and seed layer in a plasma chamber. The barrier layer and seed layer are preferably deposited in a plasma chamber having an inductive coil and a target comprising the material to be sputtered. One or more plasma gases having high molar masses relative to the target material are then introduced into the chamber to form a plasma. Preferably, the plasma gases are selected from xenon, krypton or a combination thereof.

摘要翻译： 本发明通常提供了一种用于在等离子体室中沉积保形阻挡层和种子层的铜金属化方法。 阻挡层和种子层优选沉积在具有感应线圈的等离子体室中，并且靶包括要溅射的材料。 然后将相对于靶材料具有高摩尔质量的一种或多种等离子气体引入室中以形成等离子体。 优选地，等离子体气体选自氙，氪或其组合。

公开(公告)号：US08500963B2

公开(公告)日：2013-08-06

申请号：US11778648

申请日：2007-07-17

申请人： Mengqi Ye ,  Keith A. Miller ,  Peijun Ding ,  Goichi Yoshidome ,  Rong Tao

发明人： Mengqi Ye ,  Keith A. Miller ,  Peijun Ding ,  Goichi Yoshidome ,  Rong Tao

IPC分类号： C23C14/35

CPC分类号： C23C14/0623 ,  C23C14/351 ,  C23C14/541

摘要： A plasma sputtering method for metal chalcogenides, such as germanium antimony telluride (GST), useful in forming phase-change memories. The substrate is held at a selected temperature at which the material deposits in either an amorphous or crystalline form. GST has a low-temperature amorphous range and a high-temperature crystalline range separated by a transition band of 105-120° C. Bipolar pulsed sputtering with less than 50% positive pulses of less than 10:s pulse width cleans the target while maintain the sputtering plasma. The temperature of chamber shields is maintained at a temperature favoring crystalline deposition or they may be coated with arc-spray aluminum or with crystallographically aligned copper or aluminum.

摘要翻译： 用于形成相变存储器的金属硫族化物的等离子体溅射方法，例如锗锑碲化物（GST）。 将基材保持在选定的温度，在该温度下，材料以无定形或结晶形式沉积。 GST具有低温无定形范围和105-120°C的过渡带隔离的高温结晶范围。具有小于10s脉冲宽度的小于50％正脉冲的双极脉冲溅射清洁目标，同时保持 溅射等离子体。 室屏蔽的温度保持在有利于结晶沉积的温度下，或者它们可以用电弧喷涂铝或用结晶取向的铜或铝涂覆。

公开(公告)号：US08993434B2

公开(公告)日：2015-03-31

申请号：US13226612

申请日：2011-09-07

申请人： Jick M. Yu ,  Rong Tao ,  Xinyu Fu

发明人： Jick M. Yu ,  Rong Tao ,  Xinyu Fu

IPC分类号： H01L21/4763 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089

摘要： Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

摘要翻译： 本文提供了在其上形成有一个或多个特征的基底上形成层的方法。 在一些实施例中，用于在其上形成有一个或多个特征的衬底上形成层的方法可包括在一个或多个特征内沉积晶种层; 并且蚀刻种子层以去除邻近特征的开口的种子层的至少一部分，使得种子层包括设置在靠近特征的底部的特征的侧壁的下部的第一厚度，以及第二 厚度设置在靠近特征开口的侧壁的上部，并且其中第一厚度大于第二厚度。

公开(公告)号：US08293647B2

公开(公告)日：2012-10-23

申请号：US12620818

申请日：2009-11-18

申请人： Jenn-Yue Wang ,  Hua Chung ,  Rong Tao ,  Hong Zhang

发明人： Jenn-Yue Wang ,  Hua Chung ,  Rong Tao ,  Hong Zhang

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  C25D5/022 ,  C25D5/10 ,  H01L21/2885 ,  H01L21/321 ,  H01L2221/1063

摘要： Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.

摘要翻译： 本发明的实施例一般涉及用于处理半导体衬底的装置和方法。 一个实施例提供了一种提供用于处理衬底的方法的方法，包括在其上形成有沟槽或通孔结构的衬底上形成晶种层，用有机钝化膜涂覆种子层的一部分，以及将沟槽或通孔结构浸入 电镀溶液以在未被有机钝化膜覆盖的种子层上沉积导电材料。

公开(公告)号：US20100130007A1

公开(公告)日：2010-05-27

申请号：US12620818

申请日：2009-11-18

申请人： JENN-YUE WANG ,  Hua Chung ,  Rong Tao ,  Hong Zhang

发明人： JENN-YUE WANG ,  Hua Chung ,  Rong Tao ,  Hong Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/76877 ,  C25D5/022 ,  C25D5/10 ,  H01L21/2885 ,  H01L21/321 ,  H01L2221/1063

摘要： Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.

摘要翻译： 本发明的实施例一般涉及用于处理半导体衬底的装置和方法。 一个实施例提供了一种提供用于处理衬底的方法的方法，包括在其上形成有沟槽或通孔结构的衬底上形成晶种层，用有机钝化膜涂覆种子层的一部分，以及将沟槽或通孔结构浸入 电镀溶液以在未被有机钝化膜覆盖的种子层上沉积导电材料。

公开(公告)号：US20050006222A1

公开(公告)日：2005-01-13

申请号：US10495506

申请日：2002-11-14

申请人： Peijun Ding ,  Rong Tao ,  Zheng Xu ,  Daniel Lubben ,  Suraj Rengarajan ,  Michael Miller ,  Arvind Sundarrajan ,  Xianmin Tang ,  John Forster ,  Jianming Fu ,  Roderick Mosely ,  Fusen Chen ,  Praburam Gopalraja

发明人： Peijun Ding ,  Rong Tao ,  Zheng Xu ,  Daniel Lubben ,  Suraj Rengarajan ,  Michael Miller ,  Arvind Sundarrajan ,  Xianmin Tang ,  John Forster ,  Jianming Fu ,  Roderick Mosely ,  Fusen Chen ,  Praburam Gopalraja

IPC分类号： C23C14/04 ,  C23C14/34 ,  C23C14/35 ,  C23C14/56 ,  H01J37/32 ,  H01J37/34 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  C23C14/00 ,  C23C14/32 ,  C25B9/00

CPC分类号： C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

摘要： A magnetron sputter reactor (410) and its method of use, in which SIP sputtering and ICP sputtering are promoted is disclosed. In another chamber (412) an array of auxiliary magnets positioned along sidewalls (414) of a magnetron sputter reactor on a side towards the wafer from the target is disclosed. The magnetron (436) preferably is a small one having a stronger outer pole (442) of a first polarity surrounding a weaker inner pole (440) of a second polarity all on a yoke (444) and rotates about the axis (438) of the chamber using rotation means (446, 448, 450). The auxiliary magnets (462) preferably have the first polarity to draw the unbalanced magnetic field (460) towards the wafer (424), which is on a pedestal (422) supplied with power (454). Argon (426) is supplied through a valve (428). The target (416) is supplied with power (434).

摘要翻译： 公开了一种促进SIP溅射和ICP溅射的磁控溅射反应器（410）及其使用方法。 在另一个室（412）中，公开了一种辅助磁体阵列，其沿着磁控溅射反应器的侧面（414）定位，所述磁控溅射反应器在朝向晶片的一侧朝向靶。 优选地，磁控管（436）是小的，其具有第一极性的更强的外极（442），其具有围绕轭（444）的第二极性的较弱内极（440），并且围绕轴线（438）旋转 所述室使用旋转装置（446,448,450）。 辅助磁体（462）优选地具有第一极性，以将不平衡磁场（460）朝着被提供电力（454）的基座（422）上的晶片（424）拉出。 氩（426）通过阀（428）供应。 目标（416）被供电（434）。