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公开(公告)号：US07489123B2
公开(公告)日：2009-02-10
申请号：US11296858
申请日：2005-12-07
IPC分类号： G01R31/28
CPC分类号： G01R31/31924 , G01R31/3191
摘要： An integrated circuit for automatic calibration control of pin electronics is disclosed. The integrated circuit includes a substrate, and both pin electronics and a calibration circuit integral with the substrate. The calibration circuit is dedicated to a single channel of automatic testing equipment for a single pin of a device under test. Each sub-circuit of the pin electronics may include a replica output. The replica output is electrically coupled to the calibration circuit. The calibration circuit may include a multiplexor for receiving each of the replica outputs from the sub-circuits, such as a comparator, load and a driver, and for selectively switching between the replica outputs to determine calibration parameters for one or more levels of the sub-circuit. The calibration circuit includes a state machine capable of determining calibration parameters including offset and gain. After determining the calibration parameters, the state machine can compensate the one or more levels for each sub-circuit of the pin electronics based upon the calibration parameters.
摘要翻译： 公开了一种用于引脚电子器件的自动校准控制的集成电路。 集成电路包括基板，以及两个引脚电子器件和与基板成一体的校准电路。 校准电路专用于被测设备的单个引脚的单通道自动测试设备。 引脚电子器件的每个子电路可以包括复制输出。 复制输出电耦合到校准电路。 校准电路可以包括多路复用器，用于从子电路（例如比较器，负载和驱动器）接收副本输出中的每一个，并且用于在复制输出之间选择性地切换以确定子级的一个或多个级别的校准参数 电路 校准电路包括能够确定包括偏移和增益的校准参数的状态机。 在确定校准参数之后，状态机可以基于校准参数来补偿针脚电子器件的每个子电路的一个或多个电平。
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公开(公告)号：US06337218B1
公开(公告)日：2002-01-08
申请号：US09321921
申请日：1999-05-28
IPC分类号： H01L2166
CPC分类号： G01R1/06705 , G01R31/2831 , G01R31/311 , G01R31/312
摘要： An apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. At least one tool measures and controls deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.
摘要翻译： 一种用于测试半导体晶片结构的装置。 该装置包括至少一个测试探针。 当所述至少一个测试探针接近半导体晶片中的结构的表面时，至少一个工具测量和控制所述至少一个测试探针的减速度。
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3.发明授权公开(公告)号：US09018089B2
公开(公告)日：2015-04-28
申请号：US13221698
申请日：2011-08-30
申请人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephen A. Cohen , Stephen M. Gates , Thomas M. Shaw
发明人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephen A. Cohen , Stephen M. Gates , Thomas M. Shaw
IPC分类号： H01L21/26 , H01L21/3105 , H01L21/66 , H01L21/768
CPC分类号： H01L21/3105 , H01L21/76828 , H01L21/76829 , H01L22/14
摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。
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公开(公告)号：US5631572A
公开(公告)日：1997-05-20
申请号：US227854
申请日：1994-04-15
IPC分类号： G01R31/02 , G01R31/04 , G01R31/303 , G01R31/312 , G01R31/315
CPC分类号： G01R31/315 , G01R31/046 , G01R31/303
摘要： An apparatus and method are disclosed for testing connections between printed circuit boards and components mounted thereon. A conductive loop is formed by forward biasing a parasitic diode that is inherently present between an integrated circuit (IC) lead and the ground plane of the IC. A magnetic field is created by an antenna mounted above the component to be tested. When the antenna is energized by an RF source, a voltage is induced in the conductive loop if the loop is continuous, i.e., if all of the connections are properly made. The voltage in the loop is measured and compared to a selected threshold to produce a pass/fail indication. This tester may be implemented as an improvement to a standard type of "bed-of-nails" printed circuit board tester. The antenna may be implemented as an array of spiral loop antennas, with adjacent antennas producing magnetic fields that are 90 degrees out of phase with each other.
摘要翻译： 公开了一种用于测试安装在其上的印刷电路板和组件之间的连接的装置和方法。 通过正向偏置固有地存在于集成电路（IC）引线和IC的接地平面之间的寄生二极管来形成导通回路。 磁场由安装在待测组件上方的天线产生。 当天线被RF源激励时，如果环路是连续的，即如果所有的连接都被适当地制造，则在导电回路中感应出电压。 测量回路中的电压并将其与选定的阈值进行比较，以产生通过/失败指示。 该测试器可以被实现为对标准类型的“床钉”印刷电路板测试器的改进。 天线可以被实现为螺旋环形天线的阵列，其中相邻的天线产生彼此相差90度的磁场。
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公开(公告)号：US07755159B2
公开(公告)日：2010-07-13
申请号：US12131330
申请日：2008-06-02
IPC分类号： H01L29/00
CPC分类号： H01L21/76801 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02354 , H01L21/268 , H01L21/3122 , H01L21/31633 , H01L21/76825 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , Y10T428/249978
摘要： A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.
摘要翻译： 与现有技术的电介质膜相比，包括具有改进的绝缘性能的Si，C，O和H原子（以下称为SiCOH）的电介质膜的制造方法，包括不经受本发明的深层超导体的现有技术的SiCOH介电膜， 紫色（DUV）。 改进的性能包括减少的电流泄漏，其不会不利地影响（增加）SiCOH介电膜的介电常数。 根据本发明，通过使沉积的SiCOH电介质膜进行DUV激光退火，获得了表现出减小的电流泄漏和改进的可靠性的SiCOH电介质膜。 本发明的DUV激光退火工序可能从膜中除去弱结合的C，从而提高漏电流。
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6.发明授权Sensor structures and methods for reduction of differential-heating signal errors in integrated circuits 有权用于减少集成电路差分加热信号误差的传感器结构和方法公开(公告)号：US06714078B1
公开(公告)日：2004-03-30
申请号：US10083752
申请日：2002-02-25
申请人： Stephen A. Cohen
发明人： Stephen A. Cohen
IPC分类号： H03F345
CPC分类号： H03F3/45618 , H03F1/3211 , H03F3/45085 , H03F2200/78 , H03F2203/45652 , H03F2203/45702 , H03F2203/45722
摘要： Correction sensors and methods are provided for reduction of differential-heating signal errors along a differential signal path of an electronic circuit. An exemplary correction sensor includes first and second transistors which are coupled to different sides of the differential signal path and a differential error amplifier that couples a differential correction signal to the differential signal path in differential response to a differential error signal generated by like terminals of the first and second transistors. Bias generators are preferably included to bias at least one set of same terminals of the first and second transistors that differ from the like terminals.
摘要翻译： 提供了校正传感器和方法，用于沿着电子电路的差分信号路径减小差分加热信号误差。 示例性校正传感器包括耦合到差分信号路径的不同侧面的第一和第二晶体管，以及差分误差放大器，差分误差放大器将差分校正信号与微分响应差异响应中的差分信号路径耦合到由 第一和第二晶体管。 优选地包括偏置发生器以偏置与类似端子不同的第一和第二晶体管的至少一组相同的端子。
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公开(公告)号：US06313682B1
公开(公告)日：2001-11-06
申请号：US09457235
申请日：1999-12-08
IPC分类号： H03K300
CPC分类号： H03K17/667 , H03K17/165
摘要： A shaped pulse generation circuit for applications such as automatic test equipment pin drivers employs an active feedback circuit that adds a pre-emphasis to the output pulses, thereby compensating for the effect of the transmission system between the pin driver and the device under test. Current pulses are applied to the pin driver output transistors in conjunction with the production of rising and falling output pulse edges to produce edge overshoots that are mitigated during pulse transit to the device under test. The driver circuit together with the pre-emphasis active feedback circuit can be integrated onto a single chip, with an additional programming circuit employed to control the amount of pre-emphasis.
摘要翻译： 用于诸如自动测试设备引脚驱动器的应用的成形脉冲发生电路采用有源反馈电路，其对输出脉冲增加预加重，从而补偿引脚驱动器和被测器件之间的传输系统的影响。 结合产生上升和下降的输出脉冲边沿，电流脉冲被施加到引脚驱动器输出晶体管，以产生在脉冲传送到被测器件期间减轻的边沿过冲。 驱动电路与预加重有源反馈电路一起可以集成到单个芯片上，另外还有一个用于控制预加重量的编程电路。
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公开(公告)号：US07560794B2
公开(公告)日：2009-07-14
申请号：US11693409
申请日：2007-03-29
IPC分类号： H01L29/00
CPC分类号： H01L21/76801 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02354 , H01L21/268 , H01L21/3122 , H01L21/31633 , H01L21/76825 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , Y10T428/249978
摘要： A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.
摘要翻译： 与现有技术的电介质膜相比，包括具有改进的绝缘性能的Si，C，O和H原子（以下称为SiCOH）的电介质膜的制造方法，包括不经受本发明的深超极化的现有技术的SiCOH介电膜， 紫色（DUV）。 改进的性能包括减少的电流泄漏，其不会不利地影响（增加）SiCOH介电膜的介电常数。 根据本发明，通过使沉积的SiCOH电介质膜进行DUV激光退火，获得了表现出减小的电流泄漏和改进的可靠性的SiCOH电介质膜。 本发明的DUV激光退火工序可能从膜中除去弱结合的C，从而提高漏电流。
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公开(公告)号：US07106041B1
公开(公告)日：2006-09-12
申请号：US10868580
申请日：2004-06-14
申请人： Stephen A. Cohen
发明人： Stephen A. Cohen
IPC分类号： G05F3/16
CPC分类号： G05F3/265
摘要： A current mirror includes an output stage that responds to a change in mirror output voltage with a change in output stage current, and an output compensation stage that, in response to the change in output stage current, introduces an output compensation current to oppose a change in mirror output current resulting from the change in output stage current.
摘要翻译： 电流镜包括输出级，其响应输出级电流变化对镜像输出电压的变化;以及输出补偿级，响应于输出级电流的变化，引入输出补偿电流以反对变化 在输出级电流变化产生的镜像输出电流中。
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公开(公告)号：US5559367A
公开(公告)日：1996-09-24
申请号：US273689
申请日：1994-07-12
申请人： Stephen A. Cohen , Daniel C. Edelstein , Alfred Grill , Jurij R. Paraszczak , Vishnubhai V. Patel
发明人： Stephen A. Cohen , Daniel C. Edelstein , Alfred Grill , Jurij R. Paraszczak , Vishnubhai V. Patel
IPC分类号： H01L21/8238 , H01L21/314 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/092 , H01L31/0312
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02274 , H01L23/5329 , H01L2924/0002
摘要： The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.
摘要翻译： 本发明涉及半导体器件，其包括作为其结构元件之一的类金刚石碳作为绝缘体，用于将集成电路芯片上的一个或多个级别的导体间隔开。 本发明还涉及一种形成一体结构的方法及其制造的一体结构。 本发明还提供了一种用于从含有这种层的衬底选择性地离子蚀刻类金刚石碳层的方法。
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