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公开(公告)号：US20060069903A1
公开(公告)日：2006-03-30
申请号：US10953771
申请日：2004-09-30
IPC分类号： G06F9/00
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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2.发明申请Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit 有权用于动态地配置用于集成电路的热管理的工作点的方法，系统和装置公开(公告)号：US20050091548A1
公开(公告)日：2005-04-28
申请号：US10696469
申请日：2003-10-28
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.
摘要翻译： 通过定义工作电压和频率范围来定义集成器件的热操作模式的方法和电路。
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3.发明授权Method and apparatus for establishing safe processor operating points in connection with a secure boot 有权用于建立与安全引导相关的安全处理器操作点的方法和装置公开(公告)号：US07370189B2
公开(公告)日：2008-05-06
申请号：US10953771
申请日：2004-09-30
IPC分类号： G06F9/00
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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公开(公告)号：US20070011477A1
公开(公告)日：2007-01-11
申请号：US11521649
申请日：2006-09-15
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.
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公开(公告)号：US20070157036A1
公开(公告)日：2007-07-05
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译： 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US08892861B2
公开(公告)日：2014-11-18
申请号：US13365096
申请日：2012-02-02
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
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公开(公告)号：US08707062B2
公开(公告)日：2014-04-22
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，处理器包括第一处理器核心，第二处理器核心和高速缓冲存储器。 第一处理器核心是保存第一处理器核心的状态并进入第一处理器核心断电的模式。 第二处理器核心是保存第二处理器核心的状态并进入其中第二处理器核心断电的模式。 当第一个处理器内核关闭电源时，缓存内存将被供电。 第一处理器核心是响应于第一处理器核心转换到第一处理器核心供电的模式来恢复第一处理器核心的保存状态。 第二处理器核心是响应于第二处理器核心转换到第二处理器核心供电的模式来恢复第二处理器核心的保存状态。 还公开了其他实施例。
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公开(公告)号：US20130013909A1
公开(公告)日：2013-01-10
申请号：US13620119
申请日：2012-09-14
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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9.发明申请公开(公告)号：US20110179295A1
公开(公告)日：2011-07-21
申请号：US13074871
申请日：2011-03-29
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译： 本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。 在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。 一些实施例可以生成寄存器来维护关于各种功率状态的信息。 在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。 描述其他实施例。
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10.发明授权公开(公告)号：US07516342B2
公开(公告)日：2009-04-07
申请号：US11322606
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译： 本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。 在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。 一些实施例可以生成寄存器来维护关于各种功率状态的信息。 在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。 描述其他实施例。
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