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公开(公告)号：US20060069903A1
公开(公告)日：2006-03-30
申请号：US10953771
申请日：2004-09-30
IPC分类号： G06F9/00
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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2.发明申请Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit 有权用于动态地配置用于集成电路的热管理的工作点的方法，系统和装置公开(公告)号：US20050091548A1
公开(公告)日：2005-04-28
申请号：US10696469
申请日：2003-10-28
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.
摘要翻译： 通过定义工作电压和频率范围来定义集成器件的热操作模式的方法和电路。
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公开(公告)号：US20070011477A1
公开(公告)日：2007-01-11
申请号：US11521649
申请日：2006-09-15
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.
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4.发明授权Method and apparatus for establishing safe processor operating points in connection with a secure boot 有权用于建立与安全引导相关的安全处理器操作点的方法和装置公开(公告)号：US07370189B2
公开(公告)日：2008-05-06
申请号：US10953771
申请日：2004-09-30
IPC分类号： G06F9/00
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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公开(公告)号：US20070157036A1
公开(公告)日：2007-07-05
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译： 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US08516285B2
公开(公告)日：2013-08-20
申请号：US13074871
申请日：2011-03-29
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
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公开(公告)号：US20130013945A1
公开(公告)日：2013-01-10
申请号：US13619998
申请日：2012-09-14
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译： 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US20090024799A1
公开(公告)日：2009-01-22
申请号：US11880357
申请日：2007-07-20
IPC分类号： G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3275 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F2212/1024 , G06F2212/1028 , G06F2212/1048 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
摘要翻译： 根据至少一个实施例的在低功率模式下保持缓存信息的技术。 在一个实施例中，存储在处理器的本地高速缓存中的信息在处理器被置于低功率模式之前被保存到共享高速缓存，使得其他处理器可以从共享高速缓存访问信息，而不是使低功率模式处理器从 低功耗模式来访问其本地缓存。
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9.发明申请Method, apparatus, and system for increasing single core performance in a multi-core microprocessor 有权用于增加多核微处理器中单核性能的方法，装置和系统公开(公告)号：US20080005592A1
公开(公告)日：2008-01-03
申请号：US11477751
申请日：2006-06-28
申请人： Jose Allarey , Varghese George , Sanjeev Jahagirdar , Oren Lamdan
发明人： Jose Allarey , Varghese George , Sanjeev Jahagirdar , Oren Lamdan
IPC分类号： G06F1/00
CPC分类号： G06F1/206
摘要： A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.
摘要翻译： 一种使多核处理器中的至少一个活动核心能够在较高工作点运行并且多核处理器中的至少一个其他核心处于空闲状态的方法，系统和装置。 当空闲磁芯退出空闲状态时，在滞后计时器到期后，工作点可能会减少。
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公开(公告)号：US07149645B2
公开(公告)日：2006-12-12
申请号：US11024679
申请日：2004-12-30
摘要： A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.
摘要翻译： 一种用于连续监测位于热点处的多个热传感器的装置和方法。 传感器连接到位于模具周边的传感器循环和选择块。 传感器选择块的输出转换为数字温度代码。 基于数字温度代码，热事件触发各种热控制。 热事件触发器可以是软件可编程的，提供灵活的温度管理。
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