公开(公告)号：US20110279125A1

公开(公告)日：2011-11-17

申请号：US12781514

申请日：2010-05-17

申请人： Stephen W. Bedell ,  Christopher D' Emic ,  Hongbo Peng ,  Sufi Zafar

发明人： Stephen W. Bedell ,  Christopher D' Emic ,  Hongbo Peng ,  Sufi Zafar

IPC分类号： G01N27/06 ,  H01L21/02

CPC分类号： B82Y15/00 ,  G01N27/02 ,  G01N27/4145 ,  G01N33/48721

摘要： A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.

摘要翻译： 使用包含嵌入在纳米孔中的场效应晶体管（FET）的传感器的方法包括将传感器放置在包含生物分子和脱氧核糖核酸（DNA）中的至少一种的电解质中; 将电极放置在电解质中; 将所述子阈值状态中的栅极电压施加到所述电极; 将漏极电压施加到FET的漏极; 将源电压施加到FET的源极; 响应于生物分子和通过纳米孔的DNA中的至少一个，检测传感器中的漏极电流的变化。

公开(公告)号：US08828138B2

公开(公告)日：2014-09-09

申请号：US12781514

申请日：2010-05-17

申请人： Stephen W. Bedell ,  Christopher D'Emic ,  Hongbo Peng ,  Sufi Zafar

发明人： Stephen W. Bedell ,  Christopher D'Emic ,  Hongbo Peng ,  Sufi Zafar

IPC分类号： C30B1/06 ,  G01N27/414 ,  B82Y15/00

CPC分类号： B82Y15/00 ,  G01N27/02 ,  G01N27/4145 ,  G01N33/48721

摘要： A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.

摘要翻译： 使用包含嵌入在纳米孔中的场效应晶体管（FET）的传感器的方法包括将传感器放置在包含生物分子和脱氧核糖核酸（DNA）中的至少一种的电解质中; 将电极放置在电解质中; 将所述子阈值状态中的栅极电压施加到所述电极; 将漏极电压施加到FET的漏极; 将源电压施加到FET的源极; 响应于生物分子和通过纳米孔的DNA中的至少一个，检测传感器中的漏极电流的变化。

公开(公告)号：US08409867B2

公开(公告)日：2013-04-02

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00 ,  G01N33/48

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20130005156A1

公开(公告)日：2013-01-03

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/324

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

公开(公告)号：US20120001614A1

公开(公告)日：2012-01-05

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01R1/30 ,  G01N27/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US08052931B2

公开(公告)日：2011-11-08

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20110163812A1

公开(公告)日：2011-07-07

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： H03F3/16

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20080293259A1

公开(公告)日：2008-11-27

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

IPC分类号： H01L21/263

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

公开(公告)号：US20080191292A1

公开(公告)日：2008-08-14

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/49 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US20080017936A1

公开(公告)日：2008-01-24

申请号：US11477707

申请日：2006-06-29

申请人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/78

摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.

摘要翻译： 提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。 公开了nFET和/或pFET结构。 根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在 电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。