公开(公告)号：US5475329A

公开(公告)日：1995-12-12

申请号：US176815

申请日：1994-01-04

申请人： Steven C. Jones ,  Wayne T. Chen

发明人： Steven C. Jones ,  Wayne T. Chen

IPC分类号： H03K17/04 ,  H03K17/042 ,  H03K17/082 ,  H03K17/695 ,  H03K3/00 ,  H03K5/08

CPC分类号： H03K17/04206 ,  H03K17/0822

摘要： A turn-off circuit is disclosed that includes a turn-off device (14) having a first current path connected to a first node, a second current path connected to a second node and an input. A control circuit (16) has an output connected to the input of the turn-off device (14) and has an input. A hold-off device (18) has an output connected to the first node and an input. Together, the turn-off device (14), the control circuit (16) and the hold-off device (18) comprise a turn-off circuit (20). A control signal CONTROL 2 is connected to the input of the control circuit (16), and a control signal CONTROL 3 is connected to the input of the hold-off device (18).

摘要翻译： 公开了一种关断电路，其包括具有连接到第一节点的第一电流路径，连接到第二节点的第二电流路径和输入的关断装置（14）。 控制电路（16）具有连接到关断装置（14）的输入并具有输入的输出。 保持装置（18）具有连接到第一节点和输入的输出。 关断装置（14），控制电路（16）和保持装置（18）一起包括关断电路（20）。 控制信号CONTROL2连接到控制电路（16）的输入，并且控制信号CONTROL3连接到保持装置（18）的输入端。

公开(公告)号：US5777502A

公开(公告)日：1998-07-07

申请号：US693765

申请日：1996-08-07

申请人： Wayne T. Chen ,  Steven C. Jones ,  Stephen C. Kwan

发明人： Wayne T. Chen ,  Steven C. Jones ,  Stephen C. Kwan

IPC分类号： H03K5/08 ,  H03K17/687

CPC分类号： H03K17/0822 ,  H03K2217/0036 ,  H03K2217/0063

摘要： A circuit (10) and method for protecting the gate-source elements of an FET includes a circuit (12, 13) for providing a pullup gate drive current to the gate-source elements. A voltage sensing circuit (45) senses a voltage on the gate-source elements to produce an indication if the voltage has exceeded a predetermined level. The voltage sensing circuit (45) has a zener diode (48) and a current mirror with first (52) and second (51) current flow paths. The zener diode (48) and the first flow path (52) are connected between the gate and a source of the FET. When a voltage between the gate and source of the FET exceeds the breakdown voltage of the zener diode (48) and one V.sub.gs in the current mirror, a current flows in the first flow path (52) producing a current flow in the second flow path (51). A circuit (20, 23, 62, 58, 60) reduces the pullup gate drive current in response to the current in the second flow path (51).

摘要翻译： 用于保护FET的栅极 - 源极元件的电路（10）和方法包括用于向栅极 - 源极元件提供上拉栅极驱动电流的电路（12,13）。 电压检测电路（45）感测栅极 - 源极元件上的电压，以产生电压是否超过预定电平的指示。 电压感测电路（45）具有齐纳二极管（48）和具有第一（52）和第二（51）电流流动路径的电流镜。 齐纳二极管（48）和第一流路（52）连接在栅极和FET的源极之间。 当FET的栅极和源极之间的电压超过齐纳二极管（48）的击穿电压和电流反射镜中的一个Vgs时，电流在第一流动路径（52）中流动，从而在第二流动路径 （51）。 电路（20,23,62,58,60）响应于第二流路（51）中的电流而减小上拉栅极驱动电流。

公开(公告)号：US09530555B2

公开(公告)日：2016-12-27

申请号：US13434807

申请日：2012-03-29

申请人： Ross E. Teggatz ,  Wayne T. Chen

发明人： Ross E. Teggatz ,  Wayne T. Chen

IPC分类号： H01F38/00 ,  H01F38/14 ,  H02J5/00

CPC分类号： H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/50 ,  H02J50/80 ,  H02J50/90

摘要： Wireless power transmittal apparatus and systems are disclosed in which transmitter and receiver inductors, or coils, are coupled in configurations for wirelessly transferring power and/or data among them. In preferred implementations, a plurality of non-coplanar primary side coils are provided in power transmittal apparatus for transmitting power, or power and data.

摘要翻译： 公开了无线电力传输装置和系统，其中发射机和接收机电感器或线圈以用于在它们之间无线传输功率和/或数据的配置耦合。 在优选实施方案中，在功率传输装置中提供多个非共面初级侧线圈，用于发射功率或功率和数据。

公开(公告)号：US09343988B2

公开(公告)日：2016-05-17

申请号：US13567039

申请日：2012-08-04

申请人： Ross E. Teggatz ,  David D. Briggs ,  Amer H. Atrash ,  Wayne T. Chen

发明人： Ross E. Teggatz ,  David D. Briggs ,  Amer H. Atrash ,  Wayne T. Chen

IPC分类号： H02M3/24 ,  H02M3/338 ,  H02M1/42 ,  H02M1/00

CPC分类号： H02M3/33507 ,  H02M1/08 ,  H02M1/14 ,  H02M1/42 ,  H02M1/4225 ,  H02M3/3387 ,  H02M2001/0006 ,  H02M2001/0009 ,  H02M2001/0032 ,  H05B33/0815 ,  H05B33/0851 ,  Y02B70/126 ,  Y02B70/16

摘要： Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.

摘要翻译： 电流模式调节的电路，系统和方法包括用于接收输入信号的初级侧和用于输出输出信号的次级。 调节器跨越主要和次要侧面，通过该配置可以对输入信号进行整流，此后将其提供给输出节点作为输出信号。 在输出节点处提供电流监视器，用于将输出信号与参考值进行比较。 包括通信链路，用于向调节器的初级侧提供反馈信号以用于调节信号。

公开(公告)号：US20120087187A1

公开(公告)日：2012-04-12

申请号：US13327364

申请日：2011-12-15

申请人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith ,  Eric Blackall

发明人： Ross E. Teggatz ,  Wayne T. Chen ,  Brett Smith ,  Eric Blackall

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0408 ,  G11C16/3468 ,  G11C27/005

摘要： The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.

摘要翻译： 本发明提供了编程浮动栅极的方法。 在具有浮置参考节点和偏移减轻反馈环路的电路中使用浮动栅极隧道装置与模拟比较装置，用于迭代地编程浮动栅极或多个浮动栅极。

公开(公告)号：US07236034B2

公开(公告)日：2007-06-26

申请号：US10901833

申请日：2004-07-27

申请人： Wayne T. Chen ,  Narasimhan R. Trichy

发明人： Wayne T. Chen ,  Narasimhan R. Trichy

IPC分类号： H03H11/06

CPC分类号： H03K19/00323 ,  H03K2005/00097 ,  H03K2005/00123 ,  H04L25/0272

摘要： The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.

摘要翻译： 匹配上拉和下拉器件的自校正方案包括：用于将共模信号与高参考极限进行比较的第一比较器; 第二比较器，用于将共模信号与低参考极限进行比较; 第一触发器，其具有耦合到所述第一比较器的输出的输入; 第二触发器，具有耦合到第二比较器的输出的输入; 具有耦合到第一和第二触发器的输入的计数器; 以及由计数器的输出控制的延迟装置，其中延迟装置提供相对于上拉控制信号延迟的下拉控制信号。

公开(公告)号：US06614297B2

公开(公告)日：2003-09-02

申请号：US09900396

申请日：2001-07-06

申请人： Michael D. Score ,  Paras M. Dagli ,  Roy C. Jones, III ,  Wayne T. Chen

发明人： Michael D. Score ,  Paras M. Dagli ,  Roy C. Jones, III ,  Wayne T. Chen

IPC分类号： H03F338

CPC分类号： H03F3/2173 ,  H03F3/217 ,  H03F2200/384

摘要： A ternary modulation scheme for filterless switching amplifiers with reduced EMI reduces the common mode component of the signal by allowing only one state with zero differential voltage across the load to exist. The ternary modulation scheme is more efficient than the quaternary modulation scheme when applied to class-D filterless switching amplifiers since the gates of the power MOSFETs are being charged and discharged at only a small duty cycle instead of 50% duty cycle.

公开(公告)号：US6016002A

公开(公告)日：2000-01-18

申请号：US993820

申请日：1997-12-18

申请人： Julian Zhiliang Chen ,  Thomas A. Vrotsos ,  Wayne T. Chen

发明人： Julian Zhiliang Chen ,  Thomas A. Vrotsos ,  Wayne T. Chen

IPC分类号： H01L29/74 ,  H01L23/60 ,  H01L27/02 ,  H02H7/20 ,  H02H9/04 ,  H05F3/02 ,  H01L23/62 ,  H01L29/00 ,  H01L31/111

CPC分类号： H01L27/0262 ,  H01L27/0266 ,  H01L2924/0002

摘要： An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128) is approximately equal to the sum of the individual holding voltages for the SCRs (126, 128), which overall holding voltage is greater than the trigger voltage. Preferably, the SCR (68) is isolated from the P substrate (92) by a P-N junction which is provided by disposing the SCR (68) within an N-tank (98).

摘要翻译： 提供了用于保护集成电路（62）抵抗ESD事件的SCR（68），其具有响应于施加到集成电路（62）的功率而被自动调整到不同触发电压电平的触发电压。 提供增强型P沟道晶体管（78）用于确定触发电压。 当工作电源未被施加到集成电路（62）时，P沟道晶体管（78）阈值电压确定触发SCR（68）的电压。 当工作电源施加到集成电路（62）时，工作电压被施加到P沟道晶体管（78）的栅极，然后P沟道晶体管（78）的工作电压和阈值电压 确定SCR（68）的触发电压。 然后，形成SCR（68）的PNP和NPN晶体管对（76,80）被锁存以将受保护的信号路径（69）分流到地。 SCR（68）保持锁存，直到施加到信号路径（69）的电压落在SCR（68）的保持电压以下。 多个SCR（126,128）可以串联连接，使得SCR系列（126,128）的整体保持电压近似等于SCR的各个保持电压之和（126,128 ），其总保持电压大于触发电压。 优选地，SCR（68）通过将SCR（68）设置在N-罐（98）内而提供的P-N结与P基板（92）隔离。

公开(公告)号：US5869882A

公开(公告)日：1999-02-09

申请号：US724575

申请日：1996-09-30

申请人： Wayne T. Chen ,  Ross E. Teggatz ,  Taylor R. Efland

发明人： Wayne T. Chen ,  Ross E. Teggatz ,  Taylor R. Efland

IPC分类号： H01L29/866 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L29/866 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/66106

摘要： A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region. Structure is provided between the first and second regions for repelling majority charge carriers associated with the opposite conductivity type which can be a field plate spaced from the first tank; a portion at the surface of the first tank having the first conductivity type; or a tank, of first conductivity type disposed in the first tank, abutting the first region, extending more deeply into the first tank than does the first region and more lightly doped than the first region. In accordance with a further embodiment, the diode includes a semiconductor substrate, a first tank portion disposed in the substrate and a second tank portion disposed in the first tank portion as in the prior embodiments. A first region of first conductivity type is disposed in the second tank portion and extends into the first tank portion. A second region of opposite conductivity type more highly doped than the first tank portion is disposed in the first tank portion and spaced from the first region.

摘要翻译： 能够以比现有技术高得多的电压击穿的齐纳二极管通过提供具有设置在其中的具有相反导电类型的第一容器的第一导电类型的半导体衬底来制造。 第一罐包括相对较低和相对较高的电阻率部分，相对较低的掺杂部分将相对较高的掺杂部分与衬底隔离。 第一导电类型的第一区域设置在较高掺杂部分中，并且具有相反导电类型的第二区域和比第一容器更高掺杂的第二区域与第一区域间隔开。 在第一和第二区域之间提供结构，用于排斥与相反导电类型相关联的多数电荷载体，其可以是与第一罐间隔开的场板; 第一罐的表面上具有第一导电类型的部分; 或第一导电类型的罐，邻接第一区域，比第一区域更深地延伸到第一槽中，并且比第一区域更轻地掺杂。 根据另一实施例，二极管包括半导体衬底，设置在衬底中的第一容器部分和如先前实施例中那样设置在第一容器部分中的第二容器部分。 第一导电类型的第一区域设置在第二罐部分中并延伸到第一罐部分中。 与第一容器部分相比更高掺杂的相反导电类型的第二区域设置在第一罐部分中并与第一区域间隔开。

公开(公告)号：US5539334A

公开(公告)日：1996-07-23

申请号：US991622

申请日：1992-12-16

申请人： John S. Clapp, III ,  Wayne T. Chen

发明人： John S. Clapp, III ,  Wayne T. Chen

IPC分类号： H03K3/356 ,  H03K17/10 ,  H03K19/0185 ,  H03K19/003

CPC分类号： H03K17/102 ,  H03K3/356017 ,  H03K3/356113

摘要： A voltage level shifter circuit (10) for outputting an output high (18) and output low (18) signal is provided which accommodates multiple power supplies (12 and 22) at different relative voltage to each other. The voltage level shifter (10) includes an input stage (24) which is characterized by voltage ranges applicable to the process used to make the circuit. The voltage level shifter circuit includes an output stage (18) which is also characterized by the same voltage ranges which cannot be exceeded. The output stage outputs the translated output high (16) and output low (18) voltage signals. A clamping network (20) is employed to ensure that the output stage voltage ranges are not exceeded. The present invention implements a high voltage level shifter (10) using low voltage components by extending the breakdown capability of the voltage level shifter circuit (10) past the breakdown voltage of any single component in the circuit.

摘要翻译： 提供了用于输出高输出（18）和输出低（18）信号的电压电平移位器电路（10），其以彼此不同的相对电压容纳多个电源（12和22）。 电压电平转换器（10）包括输入级（24），其特征在于适用于用于制造电路的工艺的电压范围。 电压电平移位电路包括输出级（18），其特征还在于不能超过相同的电压范围。 输出级输出转换输出高电平（16）和输出低电平（18）电压信号。 采用夹紧网络（20）来确保不超过输出级电压范围。 本发明通过将电压电平移位器电路（10）的击穿能力延伸超过电路中任何单个部件的击穿电压来实现使用低电压分量的高电压电平转换器（10）。