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    Integrated circuit substrate that accommodates lattice mismatch stress
    5.
    发明授权
    Integrated circuit substrate that accommodates lattice mismatch stress 有权
    集成电路基板，适应晶格失配应力

    公开(公告)号：US06429466B2

    公开(公告)日：2002-08-06

    申请号：US09774199

    申请日：2001-01-29

    申请人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    发明人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    IPC分类号： H01L31072

    CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/26533

    摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

    摘要翻译： 一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

    Buried heterostructure device having integrated waveguide grating fabricated by single step MOCVD
    6.
    发明授权
    Buried heterostructure device having integrated waveguide grating fabricated by single step MOCVD 失效
    具有通过单步MOCVD制造的集成波导光栅的埋入异质结构器件

    公开(公告)号：US07941024B2

    公开(公告)日：2011-05-10

    申请号：US12207521

    申请日：2008-09-10

    申请人： David P. Bour ,  Scott W. Corzine

    发明人： David P. Bour ,  Scott W. Corzine

    IPC分类号： G02B6/10

    CPC分类号： H01S5/12 ,  B82Y20/00 ,  G02B6/131 ,  H01S5/1231 ,  H01S5/1237 ,  H01S5/2004 ,  H01S5/2009 ,  H01S5/2201 ,  H01S5/2214 ,  H01S5/227 ,  H01S5/3211 ,  H01S5/34313 ,  H01S5/34366 ,  H01S2301/173 ,  H01S2304/04

    摘要： The device is an optoelectronic device or transparent waveguide device that comprises a growth surface, a growth mask, an optical waveguide core mesa and a cladding layer. The growth mask is located on the semiconductor surface and defines an elongate growth window having a periodic grating profile. The optical waveguide core mesa is located in the growth window and has a trapezoidal cross-sectional shape. The cladding layer covers the optical waveguide core mesa and extends over at least part of the growth mask. Such devices are fabricated by providing a wafer comprising a growth surface, growing an optical waveguide core mesa on the growth surface by micro-selective area growth at a first growth temperature and covering the optical waveguide core mesa with cladding material at a second growth temperature, lower than the first growth temperature.

    摘要翻译： 该器件是包括生长表面，生长掩模，光波导核心台面和包层的光电器件或透明波导器件。 生长掩模位于半导体表面上并且限定具有周期性光栅轮廓的细长生长窗口。 光波导核心台面位于生长窗口中，具有梯形横截面形状。 包覆层覆盖光波导芯体台面并在生长掩模的至少一部分上延伸。 这样的器件通过提供包括生长表面的晶片来制造，通过在第一生长温度下的微选择性区域生长在生长表面上生长光波导核心台面并且在第二生长温度下覆盖包含材料的光波导芯台面， 低于第一生长温度。

    Buried heterostucture device having integrated waveguide grating fabricated by single step MOCVD
    8.
    发明授权
    Buried heterostucture device having integrated waveguide grating fabricated by single step MOCVD 失效
    具有通过单步MOCVD制造的集成波导光栅的埋式异质结构装置

    公开(公告)号：US07440666B2

    公开(公告)日：2008-10-21

    申请号：US11154034

    申请日：2005-06-16

    申请人： David P. Bour ,  Scott W. Corzine

    发明人： David P. Bour ,  Scott W. Corzine

    IPC分类号： G02B6/10 ,  H01S5/12

    CPC分类号： H01S5/12 ,  B82Y20/00 ,  G02B6/131 ,  H01S5/1231 ,  H01S5/1237 ,  H01S5/2004 ,  H01S5/2009 ,  H01S5/2201 ,  H01S5/2214 ,  H01S5/227 ,  H01S5/3211 ,  H01S5/34313 ,  H01S5/34366 ,  H01S2301/173 ,  H01S2304/04

    摘要： The device is an optoelectronic device or transparent waveguide device that comprises a growth surface, a growth mask, an optical waveguide core mesa and a cladding layer. The growth mask is located on the semiconductor surface and defines an elongate growth window having a periodic grating profile. The optical waveguide core mesa is located in the growth window and has a trapezoidal cross-sectional shape. The cladding layer covers the optical waveguide core mesa and extends over at least part of the growth mask. Such devices are fabricated by providing a wafer comprising a growth surface, growing an optical waveguide core mesa on the growth surface by micro-selective area growth at a first growth temperature and covering the optical waveguide core mesa with cladding material at a second growth temperature, lower than the first growth temperature.

    摘要翻译： 该器件是包括生长表面，生长掩模，光波导核心台面和包层的光电器件或透明波导器件。 生长掩模位于半导体表面上并且限定具有周期性光栅轮廓的细长生长窗口。 光波导核心台面位于生长窗口中，具有梯形横截面形状。 包覆层覆盖光波导芯体台面并在生长掩模的至少一部分上延伸。 这样的器件通过提供包括生长表面的晶片来制造，通过在第一生长温度下的微选择性区域生长在生长表面上生长光波导核心台面并且在第二生长温度下覆盖包含材料的光波导芯台面， 低于第一生长温度。

    Nitride semiconductor vertical cavity surface emitting laser
    9.
    发明授权
    Nitride semiconductor vertical cavity surface emitting laser 失效
    氮化物半导体垂直腔表面发射激光器

    公开(公告)号：US07352788B2

    公开(公告)日：2008-04-01

    申请号：US11203699

    申请日：2005-08-15

    申请人： Scott W. Corzine ,  David P. Bour

    发明人： Scott W. Corzine ,  David P. Bour

    IPC分类号： H01S5/00

    CPC分类号： H01S5/0424 ,  B82Y20/00 ,  H01S5/18341 ,  H01S5/18369 ,  H01S5/18383 ,  H01S5/20 ,  H01S5/34333 ,  H01S2304/12

    摘要： In one aspect, a VCSEL includes a base region that has a vertical growth part laterally adjacent a first optical reflector and a lateral growth part that includes nitride semiconductor material vertically over at least a portion of the first optical reflector. An active region has at least one nitride semiconductor quantum well vertically over at least a portion of the lateral growth part of the base region and includes a first dopant of a first electrical conductivity type. A contact region includes a nitride semiconductor material laterally adjacent the active region and a second dopant of a second electrical conductivity type opposite the first electrical conductivity type. A second optical reflector is vertically over the active region and forms with the first optical reflector a vertical optical cavity overlapping at least a portion of the at least one quantum well of the active region. A method of fabricating a VCSEL also is described.

    摘要翻译： 在一个方面，VCSEL包括具有垂直生长部分的横向邻近于第一光学反射器的基底区域和在第一光学反射体的至少一部分上方垂直包括氮化物半导体材料的横向生长部分。 有源区域在基极区域的横向生长部分的至少一部分上垂直地具有至少一个氮化物半导体量子阱，并且包括第一导电类型的第一掺杂物。 接触区域包括横向邻近有源区的氮化物半导体材料和与第一导电类型相反的第二导电类型的第二掺杂剂。 第二光学反射器垂直于有源区域并且与第一光学反射器形成垂直的光学腔，其与有源区的至少一个量子阱的至少一部分重叠。 还描述了制造VCSEL的方法。

    Electroabsorption modulator
    10.
    发明授权
    Electroabsorption modulator 有权
    电吸收调制器

    公开(公告)号：US07142342B2

    公开(公告)日：2006-11-28

    申请号：US10453376

    申请日：2003-06-02

    申请人： David P. Bour ,  Ashish Tandon ,  Scott W. Corzine ,  Chaokun Lin

    发明人： David P. Bour ,  Ashish Tandon ,  Scott W. Corzine ,  Chaokun Lin

    IPC分类号： G02F1/03 ,  G02F1/07

    CPC分类号： B82Y20/00 ,  G02F1/01708 ,  G02F2001/0157

    摘要： The electroabsorption modulator comprises a p-i-n junction structure that includes an active layer, a p-type cladding layer and an n-type cladding layer with the active layer sandwiched between the cladding layers. The electroabsorption modulator additionally comprises a quantum well structure located within the active layer. The p-type cladding layer comprises a layer of heavily-doped low-diffusivity p-type semiconductor material located adjacent the active layer that reduces the extension of the depletion region into the p-type cladding layer when a reverse bias is applied to the electroabsorption modulator. The reduced extension increases the strength of the electric field applied to the quantum well structure by a given reverse bias voltage. The increased field strength increases the extinction ratio of the electroabsorption modulator.

    摘要翻译： 电吸收调制器包括p-i-n结结构，其包括有源层，p型包层和n型包覆层，活性层夹在包层之间。 电吸收调制器还包括位于有源层内的量子阱结构。 p型包覆层包括位于有源层附近的重掺杂低扩散性p型半导体材料层，当将反向偏压施加到电吸收时减少耗尽区的扩展到p型覆层 调制器。 缩小的延伸通过给定的反向偏置电压增加施加到量子阱结构的电场的强度。 增加的场强提高了电吸收调制器的消光比。