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公开(公告)号：US20090280649A1
公开(公告)日：2009-11-12
申请号：US11890790
申请日：2007-08-06
申请人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
发明人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
IPC分类号： H01L21/44 , C25D17/00 , H01L21/306
CPC分类号： C25D17/14 , B23H5/08 , C25D5/02 , C25D5/06 , C25D5/08 , C25D5/34 , C25D7/123 , C25D17/001 , C25D17/06 , C25F3/16 , C25F3/30 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
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公开(公告)号：US08158532B2
公开(公告)日：2012-04-17
申请号：US11602128
申请日：2006-11-20
申请人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
发明人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
IPC分类号： H01L21/302
CPC分类号： C25D17/14 , B23H5/08 , C25D5/02 , C25D5/06 , C25D5/08 , C25D5/34 , C25D7/123 , C25D17/001 , C25D17/06 , C25F3/16 , C25F3/30 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
摘要翻译： 电镀加速器选择性地施加到基本上未填充的宽（例如，低纵横比特征空腔）上，然后进行金属电镀以填充宽特征空腔并形成压花结构，其中宽特征 在金属填充的宽特征空腔上的金属突起高于金属在场区域的高度，大多数覆盖层金属被使用非接触技术（例如化学湿法蚀刻）去除，在宽特征腔上方的金属保护金属 在一些实施例中，将金属电镀到衬底上以填充狭窄（例如，高纵横比特征腔），并且可以避免金属互连和介电绝缘层的侵蚀。 在介电层中选择性地施加电镀加速器和填充宽特征腔。
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公开(公告)号：US20090277867A1
公开(公告)日：2009-11-12
申请号：US11602128
申请日：2006-11-20
申请人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
发明人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
CPC分类号： C25D17/14 , B23H5/08 , C25D5/02 , C25D5/06 , C25D5/08 , C25D5/34 , C25D7/123 , C25D17/001 , C25D17/06 , C25F3/16 , C25F3/30 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
摘要翻译： 电镀加速器选择性地施加到基本上未填充的宽（例如，低纵横比特征空腔）上，然后进行金属电镀以填充宽特征空腔并形成压花结构，其中宽特征 在金属填充的宽特征空腔上的金属突起高于金属在场区域的高度，大多数覆盖层金属被使用非接触技术（例如化学湿法蚀刻）去除，在宽特征腔上方的金属保护金属 在一些实施例中，将金属电镀到衬底上以填充狭窄（例如，高纵横比特征腔），并且可以避免金属互连和介电绝缘层的侵蚀。 在介电层中选择性地施加电镀加速器和填充宽特征腔。
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公开(公告)号：US08470191B2
公开(公告)日：2013-06-25
申请号：US11890790
申请日：2007-08-06
申请人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
发明人： Steven T. Mayer , Mark L. Rea , Richard S. Hill , Avishai Kepten , R. Marshall Stowell , Eric G. Webb
IPC分类号： C23F1/02
CPC分类号： C25D17/14 , B23H5/08 , C25D5/02 , C25D5/06 , C25D5/08 , C25D5/34 , C25D7/123 , C25D17/001 , C25D17/06 , C25F3/16 , C25F3/30 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
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公开(公告)号：US08415261B1
公开(公告)日：2013-04-09
申请号：US13270809
申请日：2011-10-11
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
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公开(公告)号：US08257781B1
公开(公告)日：2012-09-04
申请号：US11201709
申请日：2005-08-11
申请人： Eric G. Webb , Steven T. Mayer , David Mark Dinneen , Edmund B. Minshall , Christopher M. Bartlett , R. Marshall Stowell , Mark T. Winslow , Avishai Kepten , Jingbin Feng , Norman D. Kaplan , Richard K. Lyons , John B. Alexy
发明人： Eric G. Webb , Steven T. Mayer , David Mark Dinneen , Edmund B. Minshall , Christopher M. Bartlett , R. Marshall Stowell , Mark T. Winslow , Avishai Kepten , Jingbin Feng , Norman D. Kaplan , Richard K. Lyons , John B. Alexy
IPC分类号： C23C14/00
CPC分类号： C23C18/1617 , C23C18/1632 , C23C18/1676 , C23C18/168 , C23C18/1682 , H01L21/288 , H01L21/6715 , H01L21/76841
摘要： A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.
摘要翻译： 主要储存器容纳冷反应液体。 用于处理基板的反应容器通过进料导管连接到主容器。 加热器构造成在液体进入反应容器之前加热进料管道中的反应物液体。 优选地，加热器是微波加热器。 回收管道将反应容器与主储存器连接。 优选地，再循环冷却器在液体返回到主储存器之前冷却循环管道中的反应物液体。 优选地，积聚容器集成在进料管道中，用于在反应液进入反应容器之前积聚，加热，调节和监测反应液体。 优选地，再循环蓄能器容器集成在再循环管道中，以便当反应物液体从反应容器中排出时容纳反应液体。
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公开(公告)号：US07605082B1
公开(公告)日：2009-10-20
申请号：US11251353
申请日：2005-10-13
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/44
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。
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公开(公告)号：US08043958B1
公开(公告)日：2011-10-25
申请号：US12875857
申请日：2010-09-03
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。
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公开(公告)号：US07811925B1
公开(公告)日：2010-10-12
申请号：US12184145
申请日：2008-07-31
申请人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
发明人： Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
IPC分类号： H01L21/302 , H01L21/461 , B24B7/00
CPC分类号： H01L21/7684 , C23C18/1607 , C23C18/1882 , C25D5/02 , C25D7/123 , H01L21/02074 , H01L21/288 , H01L21/2885 , H01L21/3212 , H01L21/32134 , H01L21/76831 , H01L21/76849 , H01L21/76883 , Y10S414/135
摘要： Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
摘要翻译： 在半导体器件中的导电线上形成覆盖层的方法的特征在于以下操作：（a）提供包括介电层的半导体衬底，所述电介质层具有（i）设置在其中的暴露的导电线（例如铜线）和（ ii）设置在其上的暴露的阻挡层; 和（b）在所述半导体衬底的至少暴露的导电线上沉积覆盖层材料。 在某些实施例中，该方法还可以包括移除设置在阻挡层和导电线上的导电层（例如，覆盖层）的至少一部分以暴露阻挡层。
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公开(公告)号：US07690324B1
公开(公告)日：2010-04-06
申请号：US11200338
申请日：2005-08-09
申请人： Jingbin Feng , Steven T. Mayer , Daniel Mark Dinneen , Edmund B. Minshall , Christopher M. Bartlett , Eric G. Webb , R. Marshall Stowell , Mark T. Winslow , Avishai Kepten , Norman D. Kaplan , Richard K. Lyons , John B. Alexy
发明人： Jingbin Feng , Steven T. Mayer , Daniel Mark Dinneen , Edmund B. Minshall , Christopher M. Bartlett , Eric G. Webb , R. Marshall Stowell , Mark T. Winslow , Avishai Kepten , Norman D. Kaplan , Richard K. Lyons , John B. Alexy
IPC分类号： B05C11/02
CPC分类号： C23C18/1619 , H01L21/288 , H01L21/6715 , H01L21/76841
摘要： During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.
摘要翻译： 在衬底表面的流体处理期间，包含衬底晶片的载体/晶片组件封闭微孔容器的顶部。 载体/晶片组件和容器壁限定了用处理流体例如化学镀溶液填充的薄封闭处理体积。 薄流体处理体积通常具有在约100ml至500ml范围内的体积。 优选地，将容器加热并且将处理流体在被注入容器之前被预热。 优选地，薄封闭流体处理体积中的流体的化学组成，温度和其它性质是动态可变的。 冲洗屏和冲洗喷嘴位于容器上方。 漂洗位置的载体/晶片组件基本上封闭了冲洗屏蔽的顶部。
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