公开(公告)号：US10529616B2

公开(公告)日：2020-01-07

申请号：US15775924

申请日：2016-11-15

申请人： SUNEDISON SEMICONDUCTOR LIMITED ,  Charles R. Lottes

发明人： Gang Wang ,  Charles R. Lottes ,  Sasha Kweskin

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L27/146

摘要： A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

公开(公告)号：US20190181036A9

公开(公告)日：2019-06-13

申请号：US15574009

申请日：2016-05-18

申请人： SunEdison Semiconductor Limited

发明人： Gang Wang ,  Shawn George Thomas

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/3065

CPC分类号： H01L21/76256 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/3065 ,  H01L21/76251

摘要： The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

公开(公告)号：US20180294182A1

公开(公告)日：2018-10-11

申请号：US15574054

申请日：2016-05-23

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Gang Wang ,  Shawn George Thomas

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3065

摘要： The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium option ally with silicon.

公开(公告)号：US20180233420A1

公开(公告)日：2018-08-16

申请号：US15893055

申请日：2018-02-09

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Rapoport ,  Srikanth Kommu ,  Igor Peidous ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/66 ,  H01L23/66

CPC分类号： H01L22/14 ,  G01R31/2648 ,  H01L22/20 ,  H01L23/66 ,  H01L27/12

摘要： Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

公开(公告)号：US20180158721A1

公开(公告)日：2018-06-07

申请号：US15828534

申请日：2017-12-01

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Jeffery L. Libbert ,  Qingmin Liu ,  Gang Wang ,  Andrew M. Jones

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L23/18

摘要： A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

公开(公告)号：US20180114720A1

公开(公告)日：2018-04-26

申请号：US15727723

申请日：2017-10-09

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Gang Wang ,  Jeffrey L. Libbert ,  Shawn George Thomas ,  Qingmin Liu

IPC分类号： H01L21/762 ,  H01L27/12 ,  H01L21/02

摘要： A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

公开(公告)号：US20150378372A1

公开(公告)日：2015-12-31

申请号：US14318111

申请日：2014-06-27

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Benno Orschel ,  Arash Abedijaberi ,  Gang Wang ,  Ellen Torack

IPC分类号： G05D23/19 ,  G05B19/418

CPC分类号： G05B19/418 ,  G05B2219/45032 ,  G05D23/1917

摘要： A method for controlling temperatures in an epitaxial reactor for use in a wafer-production process is provided. The method is implemented by a computing device coupled to a memory. The method includes transmitting, to a heating device in a first zone of the epitaxial reactor, an output power instruction representing a base output power. The method additionally includes determining an actual time period for a temperature in the first zone of the epitaxial reactor to reach a target temperature, determining a difference between the actual time period and a reference time period, determining an output power offset based on the difference, and storing the output power offset in the memory in association with the heating device.

摘要翻译： 提供了一种用于控制用于晶片生产过程的外延反应器中的温度的方法。 该方法由耦合到存储器的计算设备来实现。 该方法包括向外延反应堆的第一区域中的加热装置传送表示基本输出功率的输出功率指令。 该方法还包括确定外延反应堆的第一区域中的温度达到目标温度的实际时间周期，确定实际时间段与基准时间段之间的差值，基于该差异确定输出功率偏移量， 以及将所述输出功率偏移与所述加热装置相关联地存储在所述存储器中。

公开(公告)号：US10483379B2

公开(公告)日：2019-11-19

申请号：US15867860

申请日：2018-01-11

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Qingmin Liu ,  Gang Wang

IPC分类号： H01L29/66 ,  H01L21/763 ,  H01L21/02 ,  H01L29/20 ,  H01L21/304 ,  H01L21/324 ,  H01L29/792 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L21/762

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

公开(公告)号：US10468295B2

公开(公告)日：2019-11-05

申请号：US15828534

申请日：2017-12-01

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Jeffery L. Libbert ,  Qingmin Liu ,  Gang Wang ,  Andrew M. Jones

IPC分类号： H01L23/00 ,  H01L21/762 ,  H01L21/02 ,  H01L23/18 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

摘要： A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

公开(公告)号：US10468294B2

公开(公告)日：2019-11-05

申请号：US16077142

申请日：2017-01-31

申请人： SUNEDISON SEMICONDUCTOR LIMITED ,  Igor Peidous

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/30 ,  H01L21/46 ,  H01L29/04 ,  H01L31/036 ,  H01L21/762 ,  H01L21/02 ,  H01L21/28

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.