公开(公告)号：US07800162B2

公开(公告)日：2010-09-21

申请号：US12235689

申请日：2008-09-23

申请人： Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

发明人： Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

IPC分类号： H01L29/94

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

摘要： A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

摘要翻译： 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US20080211057A1

公开(公告)日：2008-09-04

申请号：US12003973

申请日：2008-01-04

申请人： Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

发明人： Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

IPC分类号： H01L29/40

CPC分类号： H01L27/10876 ,  H01L27/10891

摘要： Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

摘要翻译： 提供一种具有掩埋字线结构的半导体器件，其中栅极电极和字线可以被掩埋在衬底内以降低半导体器件的高度并且减少由来自应用的氯离子引起的氧化物层的劣化 的TiN金属栅极，以及制造半导体器件的方法。 半导体器件可以包括由器件隔离层限定的半导体衬底，并且包括有源区，包括沟槽和一个或多个凹陷通道，沟槽表面上的栅极隔离层，栅极表面上的栅极电极层 隔离层以及沟槽可以埋在栅电极层的表面上的字线。

公开(公告)号：US20120061763A1

公开(公告)日：2012-03-15

申请号：US13224427

申请日：2011-09-02

申请人： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

发明人： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L21/764 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

摘要翻译： 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US06602782B2

公开(公告)日：2003-08-05

申请号：US09862937

申请日：2001-05-22

申请人： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

发明人： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole. A metal liner is then formed on a portion of the electrically conductive seed layer that defines a sidewall of the constricted contact hole. Next, a metal interconnect layer is reflowed into the constricted contact hole to thereby fill and bury the contact hole.

摘要翻译： 形成金属互连的方法包括在基板上形成其中具有接触孔的电绝缘层。 还进行步骤以形成导电种子层。 种子层在接触孔的侧壁上延伸，并且在邻近接触孔延伸的电绝缘层的上表面的一部分上延伸。 种子层沿着侧壁的上部足够厚，并且沿着侧壁的下部足够薄，接触孔的上部被种子层部分地收缩，从而限定了收缩的接触孔。 在种子层的在收缩的接触孔外延伸的部分上沉积抗成核层。 收缩的接触孔用作掩模以抑制邻接于缩小的接触孔的底部的防着色层的沉积。 然后在导电种子层的限定收缩的接触孔的侧壁的部分上形成金属衬垫。 接下来，将金属互连层回流到收缩的接触孔中，从而填充并埋入接触孔。

公开(公告)号：US08536652B2

公开(公告)日：2013-09-17

申请号：US13224427

申请日：2011-09-02

申请人： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

发明人： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC分类号： H01L29/78

CPC分类号： H01L21/764 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

摘要翻译： 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US06399457B2

公开(公告)日：2002-06-04

申请号：US09862733

申请日：2001-05-21

申请人： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

发明人： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  H01L21/31604 ,  H01L27/1085 ,  Y10S438/915 ,  Y10S438/919

摘要： A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

摘要翻译： 一种具有电容器的半导体器件。 电容器包括第一电极，由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序堆叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层中的每一个具有TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构，因此在750℃或更低的温度下进行形成第二电极之后的退火，从而降低电介质层的等效氧化物厚度 。

公开(公告)号：US06261890B1

公开(公告)日：2001-07-17

申请号：US09209651

申请日：1998-12-10

申请人： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

发明人： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

IPC分类号： H01L218234

CPC分类号： H01L28/60 ,  H01L21/31604 ,  H01L27/1085 ,  Y10S438/915 ,  Y10S438/919

摘要： The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

摘要翻译： 半导体器件的电容器包括第一电极，由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序层叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层是TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构，因此在形成第二电极之后的退火在750℃以下进行，以避免增加电介质层的等效氧化物厚度。

公开(公告)号：US07790591B2

公开(公告)日：2010-09-07

申请号：US12270014

申请日：2008-11-13

申请人： Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

发明人： Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/31616 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31604

摘要： Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

摘要翻译： 提供了制造半导体器件的方法，包括在半导体衬底上的栅极绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层，在隔离绝缘层上形成电极层。 阻挡绝缘层可以通过在第一温度下形成下部金属氧化物层并在低于第一温度的第二温度下在下部金属氧化物层上形成上部金属氧化物层而形成。

公开(公告)号：US06953741B2

公开(公告)日：2005-10-11

申请号：US10634168

申请日：2003-08-05

申请人： Eun-ae Chung ,  Myoung-bum Lee ,  Beom-jun Jim

发明人： Eun-ae Chung ,  Myoung-bum Lee ,  Beom-jun Jim

IPC分类号： H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/04

CPC分类号： H01L21/28525 ,  H01L21/28512 ,  H01L21/76877 ,  H01L21/76886

摘要： Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

摘要翻译： 通过对半导体器件的层间电介质进行构图以形成露出第一杂质型硅基区域的接触孔来提供制造半导体器件的接触的方法。 暴露的硅基区域掺杂含有第一杂质类型的元素的气体，并且接触孔形成在接触孔中。 还提供了一种半导体器件的接触结构，其包括半导体器件的层间电介质，其具有在其中形成的接触孔，其暴露第一杂质类型的硅基区域。 在暴露的硅基区域中提供第一杂质类型的δ掺杂区域。 在接触孔和δ掺杂区域上提供接触塞。

公开(公告)号：US06573147B2

公开(公告)日：2003-06-03

申请号：US10055260

申请日：2001-10-26

申请人： Kwang-jin Moon ,  Hee-sook Park ,  Myoung-bum Lee

发明人： Kwang-jin Moon ,  Hee-sook Park ,  Myoung-bum Lee

IPC分类号： H01L21331

CPC分类号： H01L21/76829 ,  H01L21/32051

摘要： A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.

摘要翻译： 提供具有使用裂纹保护层的接触的半导体器件及其形成方法。 由介电材料形成的裂纹保护层形成在层间电介质层上。 裂纹保护层减轻或吸收在用于形成接触插塞的导电层上产生的残余应力。 因此，可以形成接触，而不会由于残余应力而损坏层间电介质层。