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    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    1.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20150145021A1

    公开(公告)日：2015-05-28

    申请号：US14517025

    申请日：2014-10-17

    申请人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

    发明人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

    IPC分类号： H01L27/115 ,  H01L29/51

    CPC分类号： H01L27/11565 ,  H01L27/1158 ,  H01L29/66833 ,  H01L29/7926

    摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

    摘要翻译： 非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。 电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。 此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

    Vertical memory devices and methods of manufacturing the same
    2.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09012974B2

    公开(公告)日：2015-04-21

    申请号：US13246152

    申请日：2011-09-27

    申请人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    发明人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

    IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L27/115

    CPC分类号： H01L27/11582 ,  H01L29/7926

    摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

    摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，字符串选择线（SSL）和触点。 通道包括垂直部分和水平部分。 垂直部分在基本上垂直于基板的顶表面的第一方向上延伸，并且水平部分连接到垂直部分并且平行于基板的顶表面。 GSL，字线和SSL沿着第一方向依次形成在通道的垂直部分的侧壁上，并且彼此间隔开。 触点位于基板上并电连接到通道的水平部分。

    Vertical structure non-volatile memory device and method of manufacturing the same
    4.
    发明授权
    Vertical structure non-volatile memory device and method of manufacturing the same 有权
    垂直结构非易失性存储器件及其制造方法

    公开(公告)号：US08748249B2

    公开(公告)日：2014-06-10

    申请号：US13456415

    申请日：2012-04-26

    申请人： Jun-kyu Yang ,  Ki-hyun Hwang ,  Phil-ouk Nam ,  Jae-young Ahn ,  Han-mei Choi ,  Dong-chul Yoo

    发明人： Jun-kyu Yang ,  Ki-hyun Hwang ,  Phil-ouk Nam ,  Jae-young Ahn ,  Han-mei Choi ,  Dong-chul Yoo

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889

    摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

    摘要翻译： 一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。 该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。

    Methods of Manufacturing a Vertical Type Semiconductor Device
    6.
    发明申请
    Methods of Manufacturing a Vertical Type Semiconductor Device 有权
    制造垂直型半导体器件的方法

    公开(公告)号：US20120115309A1

    公开(公告)日：2012-05-10

    申请号：US13241316

    申请日：2011-09-23

    申请人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

    发明人： Dong-Chul Yoo ,  Chan-Jin Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Joon-Suk Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11582 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575

    摘要： Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

    摘要翻译： 制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。 第一模具结构形成在与第一区域相邻的基板的第二区域中。 第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。 在第一模具结构和止挡层图案上形成第二模具结构。 第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。 第二模具结构部分地覆盖止挡层图案。 形成通道图案并通过第一模具结构和第二模具结构。

    Method of manufacturing semiconductor device
    7.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07964462B2

    公开(公告)日：2011-06-21

    申请号：US12270033

    申请日：2008-11-13

    申请人： Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

    发明人： Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/3115 ,  H01L21/3162 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

    摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：在其上形成有栅极绝缘层的基板上形成电荷存储层; 使用包括金属氧化物层前体和第一氧化剂的第一反应源在电荷存储层上形成第一金属氧化物层，并且使用包括第二氧化剂的第二反应源将第一金属氧化物层改变为第二金属氧化物层 具有比第一氧化剂更大的氧化能力，并且重复形成第一金属氧化物层和将第一金属氧化物层改变为第二金属氧化物层数次以形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成电极层。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    10.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20150206900A1

    公开(公告)日：2015-07-23

    申请号：US14601496

    申请日：2015-01-21

    申请人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

    发明人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

    摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

    摘要翻译： 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。