公开(公告)号：US06492665B1

公开(公告)日：2002-12-10

申请号：US09714130

申请日：2000-11-17

申请人： Susumu Akamatsu ,  Toshitaka Hibi ,  Takehiko Ueda ,  Tadami Shimizu ,  Yoshiaki Kato ,  Tatsuya Obata ,  Toyoyuki Shimazaki

发明人： Susumu Akamatsu ,  Toshitaka Hibi ,  Takehiko Ueda ,  Tadami Shimizu ,  Yoshiaki Kato ,  Tatsuya Obata ,  Toyoyuki Shimazaki

IPC分类号： H01L31072

CPC分类号： H01L29/665 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/1045 ,  H01L29/6653 ,  H01L29/66598 ,  H01L29/7833 ,  Y10S257/90

摘要： After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.

摘要翻译： 在栅极绝缘膜之后，在Si衬底上依次形成栅电极和栅极保护层，在衬底中形成轻掺杂源极/漏极区。 第一和第二侧壁形成在栅电极的侧面上，然后通过使用这些侧壁作为掩模注入掺杂剂离子形成重掺杂的源/漏区。 在第二侧壁被选择性地去除之后，形成袋注入区域并且沉积整个保护膜。 此后，沉积层间电介质膜，形成接触孔以到达重掺杂的源/漏区，然后形成插塞电极。 由于当整个保护膜沉积时第二侧壁已经被去除，所以相邻栅电极之间的间隙没有被完全填充。因此，可以提供一种用于制造半导体器件的方法，该半导体器件有助于器件小型化而不引起短路 在栅电极和接触构件之间。

公开(公告)号：US06180472B2

公开(公告)日：2001-01-30

申请号：US09361219

申请日：1999-07-27

申请人： Susumu Akamatsu ,  Toshitaka Hibi ,  Takehiko Ueda ,  Tadami Shimizu ,  Yoshiaki Kato ,  Tatsuya Obata ,  Toyoyuki Shimazaki

发明人： Susumu Akamatsu ,  Toshitaka Hibi ,  Takehiko Ueda ,  Tadami Shimizu ,  Yoshiaki Kato ,  Tatsuya Obata ,  Toyoyuki Shimazaki

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/1045 ,  H01L29/6653 ,  H01L29/66598 ,  H01L29/7833 ,  Y10S257/90

摘要： After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.

摘要翻译： 在栅极绝缘膜之后，在Si衬底上依次形成栅电极和栅极保护层，在衬底中形成轻掺杂源极/漏极区。 第一和第二侧壁形成在栅电极的侧面上，然后通过使用这些侧壁作为掩模注入掺杂剂离子形成重掺杂的源/漏区。 在第二侧壁被选择性地去除之后，形成袋注入区域并且沉积整个保护膜。 此后，沉积层间电介质膜，形成接触孔以到达重掺杂的源/漏区，然后形成插塞电极。 由于当整个保护膜沉积时第二侧壁已经被去除，所以相邻栅电极之间的间隙没有被完全填充。因此，可以提供一种用于制造半导体器件的方法，该半导体器件有助于器件小型化而不引起短路 在栅电极和接触构件之间。

公开(公告)号：US5786273A

公开(公告)日：1998-07-28

申请号：US602575

申请日：1996-02-14

申请人： Toshitaka Hibi ,  Takatoshi Yasui ,  Hisashi Ogawa ,  Susumu Akamatsu ,  Shunsuke Kugo

发明人： Toshitaka Hibi ,  Takatoshi Yasui ,  Hisashi Ogawa ,  Susumu Akamatsu ,  Shunsuke Kugo

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/768

摘要： Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.

摘要翻译： 形成在第二层间电介质中的是第一接触孔和第二接触孔。 第一和第二接触孔各自延伸到第一级互连线。 在整个基板上形成钨以形成第一插塞，第二插头和钨层。 形成氧化硅层。 此后，进行图案化处理以形成与第一插头和顶部保护层连接的第二级互连线，并且第二插头的顶部保持暴露。 侧壁形成在第二级互连线和顶部保护层的侧表面上。 随后，形成与暴露的第二插头连接的第三级互连线。 这种布置不仅减少了接触孔形成掩模的数量，而且还减少了制造步骤的数量。 此外，第二接触孔的纵横比变低，从而实现高可靠性的半导体器件。

公开(公告)号：US07737510B2

公开(公告)日：2010-06-15

申请号：US11545427

申请日：2006-10-11

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L29/76

CPC分类号： H01L29/045 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area covering the gate electrode and the sidewall. A stress-applying stress liner film is formed to cover the gate electrode and the sidewall.

摘要翻译： 在半导体衬底的有源区上形成栅极绝缘膜和栅电极。 在栅电极的侧面上形成横截面为L形的侧壁。 源极/漏极区域形成在位于覆盖栅电极和侧壁的区域外的半导体衬底的区域中。 形成应力施加应力衬垫膜以覆盖栅电极和侧壁。

公开(公告)号：US20070096183A1

公开(公告)日：2007-05-03

申请号：US11500940

申请日：2006-08-09

申请人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

发明人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L21/336 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0629 ,  H01L27/0251 ,  H01L28/20

摘要： In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region.

摘要翻译： 在包括具有FUSI栅电极的MIS晶体管和多晶硅电阻器的半导体器件中，设置在接触形成区域中的多晶硅电阻器的一部分与栅极电极或杂质扩散区域同时被硅化。

公开(公告)号：US06660601B2

公开(公告)日：2003-12-09

申请号：US09938527

申请日：2001-08-27

申请人： Satoe Miyata ,  Hiroyuki Umimoto ,  Michikazu Matsumoto ,  Susumu Akamatsu

发明人： Satoe Miyata ,  Hiroyuki Umimoto ,  Michikazu Matsumoto ,  Susumu Akamatsu

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/7833

摘要： Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in the ion-implanted layer is set close to, and equal to or less than, a solid solubility at a process temperature for a first annealing process. Then, almost all of the dopant existing in the extended heavily doped layer is activated by performing the first annealing process. Thereafter, a sidewall and an ion-implanted layer as a prototype for a heavily doped source/drain layer are formed, and then the heavily doped source/drain layer is defined by performing a second RTA process.

公开(公告)号：US5396096A

公开(公告)日：1995-03-07

申请号：US132323

申请日：1993-10-06

申请人： Susumu Akamatsu ,  Atsuhiro Kajiya

发明人： Susumu Akamatsu ,  Atsuhiro Kajiya

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L21/76218 ,  H01L27/0928

摘要： In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

摘要翻译： 在半导体装置中，在半导体基板上设置FET和隔离，在隔离下设置沟道停止区域。 至少一个施加FET的源极区域和漏极区域的高电压的区域与沟道停止区域分离，并且在其间提供掺杂有用于调节阈值电平的杂质的第一缓冲区域。 在栅电极下方并且与隔离相邻的区域用作掺杂用于调整阈值电平的杂质的第二缓冲区域。 利用第一缓冲区域，确保漏极区域和沟道停止区域的边界处的耗尽区域，从而获得对源极/漏极区域的高电压的优异的耐久性。 利用第二缓冲区域，防止源极区域和漏极区域之间的漏电流。

公开(公告)号：US08729641B2

公开(公告)日：2014-05-20

申请号：US13293579

申请日：2011-11-10

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L27/088

CPC分类号： H01L21/823462 ,  H01L21/76224 ,  H01L21/823456 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film.

摘要翻译： 半导体器件包括第一导电类型的第一，第二和第三MIS晶体管，其分别包括半导体衬底的第一，第二和第三有源区上的第一，第二和第三栅电极，第一，第二和第三栅电极具有第一，第二和第三栅电极， 第三栅绝缘膜插入其间。 第一栅极绝缘膜由第一氧化硅膜和第一高k绝缘膜形成在第一氧化硅膜上。 第二栅极绝缘膜由第二氧化硅膜和第二高k绝缘膜形成在第二氧化硅膜上。 第三栅极绝缘膜由第三氧化硅膜和第三高k绝缘膜形成在第三氧化硅膜上。 第二氧化硅膜具有与第一氧化硅膜相同的厚度，并且具有比第三氧化硅膜更大的厚度。

公开(公告)号：US07867840B2

公开(公告)日：2011-01-11

申请号：US12796412

申请日：2010-06-08

申请人： Susumu Akamatsu ,  Masafumi Tsutsui ,  Yoshinori Takami

发明人： Susumu Akamatsu ,  Masafumi Tsutsui ,  Yoshinori Takami

IPC分类号： H01L21/8238 ,  H01L31/113

CPC分类号： H01L21/823462 ,  H01L21/823493 ,  H01L27/11

摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。

公开(公告)号：US20060150736A1

公开(公告)日：2006-07-13

申请号：US11191950

申请日：2005-07-29

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： G01H13/00 ,  G01N29/04

CPC分类号： G01H13/00 ,  G01N29/12 ,  G01N29/223 ,  G01N29/2412 ,  G01N29/348 ,  G01N2291/02854 ,  G01N2291/0289 ,  G01N2291/044 ,  G01N2291/101 ,  G01N2291/2697

摘要： An apparatus for analyzing a semiconductor device has a stage for horizontally holding a semiconductor substrate serving as a target sample to be analyzed, an ultrasonic wave transmitting/receiving unit provided above the stage to transmit and receive an ultrasonic wave, a current control unit for applying a current to the ultrasonic wave transmitting/receiving unit such that the value of the current is variable, an ultrasonic wave transmitter provided in the ultrasonic wave transmitting/receiving unit to transmit an emitted ultrasonic wave to the target sample such that the frequency of the emitted ultrasonic wave is variable with changes in the value of the current applied from the current control unit, an ultrasonic wave receiver provided in the ultrasonic wave transmitting/receiving unit to receive a reflected ultrasonic wave which is the emitted ultrasonic wave transmitted from the ultrasonic wave transmitter and reflected from the target sample, and a position control unit for controlling at least one of the stage and the ultrasonic wave transmitting/receiving unit such that either one or both of them are movable in a horizontal direction. The apparatus for analyzing a semiconductor device also analyzes the target sample based on the frequency of the reflected ultrasonic wave having an amplitude thereof enlarged by resonance between the emitted ultrasonic wave and an unanalyzed material in the target sample and on the analysis position information of the target sample obtained from the position of at least one of the stage and the ultrasonic wave transmitting/receiving unit.

摘要翻译： 用于分析半导体器件的装置具有用于水平保持用作待分析目标样本的半导体衬底的级，设置在载台上方以发送和接收超声波的超声波发射/接收单元，用于施加的电流控制单元 提供给超声波发送/接收单元的电流，使得电流值可变;超声波发射器，设置在超声波发射/接收单元中，以将发射的超声波发射到目标样本，使得发射的频率 超声波随着从电流控制单元施加的电流值的变化而变化，设置在超声波发送/接收单元中的超声波接收器接收从超声波发射器发送的发射超声波的反射超声波 并从目标样品反射，以及用于公司的位置控制单元 在舞台和超声波发射/接收单元中的至少一个上，使得它们中的一个或两个可在水平方向上移动。 用于分析半导体器件的装置还基于通过发射的超声波和目标样品中的未分析材料之间的谐振放大的振幅的反射超声波的频率以及目标的分析位置信息来分析目标样本 从舞台和超声波发送/接收单元中的至少一个的位置获得的样本。