公开(公告)号：US5129074A

公开(公告)日：1992-07-07

申请号：US409672

申请日：1989-09-20

申请人： Takashi Kikuchi ,  Hiroshi Fukuta ,  Nobuo Saito ,  Oichi Atoda

发明人： Takashi Kikuchi ,  Hiroshi Fukuta ,  Nobuo Saito ,  Oichi Atoda

IPC分类号： G06F9/44 ,  G06F17/30

CPC分类号： G06F8/313 ,  G06F17/30

摘要： A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an internal memory in which data strings are stored. The table contains a plurality of records each including a unit of data, a first index data representative of the number of units of data of a data string which the unit of data constitutes and a second index data unique to each individual data string. The processor elements access in parallel their associated tables under control of the control unit for data storage and data retrieval. The first and index data are generated by the controller for the purpose of data storage. For retrieval of data strings: a key data string is divided into units of data; retrieval keys are produced each from a combination of one of the divided units of data and a third index data representing the number of units of data of the key data string; second index data are retrieved in parallel in the tables of the data storage device with the retrieval keys so that a single second index data common to all of the retrieved second index data is found among them; and a data string corresponding to the found common second index data is outputted from the internal memory of the storage device.

摘要翻译： 一种用于存储包括数据单元的数据串的数据存储装置具有多个存储部分，每个存储部分用于在其中存储表格，为每个表格提供多个处理器元件，以及具有内部存储器的控制单元，其中数据串 被存储。 该表包含多个记录，每个记录包括数据单元，表示数据单元构成的数据串的数据单元数的第一索引数据和每个单独数据串唯一的第二索引数据。 处理器元件在用于数据存储和数据检索的控制单元的控制下并行访问其相关联的表。 第一和索引数据由控制器生成，用于数据存储。 用于检索数据串：一个关键数据串被分为数据单元; 从分割的数据单元之一的组合和表示密钥数据串的数据单元数的第三索引数据产生检索密钥; 在具有检索关键字的数据存储装置的表中并行地检索第二索引数据，使得在其中找到所有检索到的第二索引数据共同的单个第二索引数据; 并且从存储装置的内部存储器输出与所找到的公共第二索引数据相对应的数据串。

公开(公告)号：US5267198A

公开(公告)日：1993-11-30

申请号：US953747

申请日：1992-09-29

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5140681A

公开(公告)日：1992-08-18

申请号：US355680

申请日：1989-05-23

申请人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

发明人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0815 ,  G06F2212/621

摘要： A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

公开(公告)号：US5202969A

公开(公告)日：1993-04-13

申请号：US871906

申请日：1992-04-21

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G06F12/0804 ,  G11C11/4096

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5193075A

公开(公告)日：1993-03-09

申请号：US490745

申请日：1990-03-08

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G06F12/0804

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US08314493B2

公开(公告)日：2012-11-20

申请号：US12900407

申请日：2010-10-07

申请人： Takashi Kikuchi ,  Tomoaki Hashimoto ,  Tatsuya Hirai

发明人： Takashi Kikuchi ,  Tomoaki Hashimoto ,  Tatsuya Hirai

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

摘要： Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

摘要翻译： 与微电脑芯片（半导体芯片）的焊盘（电极焊盘）电连接的端子（接合引线）配置在周边部分侧的焊盘上的凸起电极（导电部件）用密封树脂（密封体）密封。 此后，密封树脂被部分地研磨（去除），使得每个凸起电极的一部分露出。 在研磨步骤之后，执行从密封树脂的前表面突出每个凸起电极的一部分的步骤。

公开(公告)号：US20120038182A1

公开(公告)日：2012-02-16

申请号：US13265392

申请日：2010-04-20

申请人： Kazuhiro Onda ,  Nobuhiro Kawamoto ,  Itaru Genpei ,  Makoto Uchikawa ,  Takashi Kikuchi ,  Hajime Ishida

发明人： Kazuhiro Onda ,  Nobuhiro Kawamoto ,  Itaru Genpei ,  Makoto Uchikawa ,  Takashi Kikuchi ,  Hajime Ishida

IPC分类号： B60J5/04

CPC分类号： B60N2/449 ,  B60J5/0443 ,  B60J5/0458 ,  B60N2/4235 ,  B60N2/42709 ,  B60N2/986 ,  B60R21/0428 ,  B62D21/157 ,  B62D25/04

摘要： Disclosed is a passenger protection device (12) for a vehicle, which protects a passenger (Mn) sitting on a seat (11) when an external force (Fs) is applied to a side surface (16a) of a vehicle body (16). The passenger protection device has a side support (14). The side support is provided on the side portion of a seat back (46), and supports the upper body (Bu) of the passenger. The side support has a deformable portion (47). The deformable portion allows the side support to be deformed by an external force having a predetermined value or more.

摘要翻译： 公开了一种用于车辆的乘客保护装置（12），当对车体（16）的侧表面（16a）施加外力（Fs）时，该乘客保护装置保护坐在座椅（11）上的乘客（Mn） 。 乘客保护装置具有侧支撑件（14）。 侧支撑件设置在座椅靠背（46）的侧部，并且支撑乘客的上身（Bu）。 侧支撑件具有可变形部分（47）。 可变形部分允许侧支撑件通过具有预定值或更大的外力而变形。

公开(公告)号：US20110308725A1

公开(公告)日：2011-12-22

申请号：US13221358

申请日：2011-08-30

申请人： Hisayasu Kaneshiro ,  Takashi Kikuchi

发明人： Hisayasu Kaneshiro ,  Takashi Kikuchi

IPC分类号： C09J7/02

CPC分类号： H05K1/0346 ,  C09J7/25 ,  C09J2479/086 ,  H05K1/0393 ,  H05K3/386 ,  H05K2201/0154 ,  H05K2201/068 ,  Y10T428/2852 ,  Y10T428/31678

摘要： Disclosed is an adhesive film having high dimensional stability which can be suitably used for two layer FPCs. Specifically, disclosed is an adhesive sheet composed of an insulting layer and an adhesive layer arranged on one side or both sides of the insulating layer. This adhesive sheet is characterized in that the insulating layer has a ratio E′2/E′1 between the storage elasticity modulus E′1 at 25° C. and the storage elasticity modulus E′2 at 380° C. of not more than 0.2 and a coefficient of thermal expansion in the MD direction of 5-15 ppm at 100-200° C. It is further characterized in that the change in the coefficient of thermal expansion of the adhesive sheet at 100-250° C. after heat treatment at 380° C. for 30 second under tension of 20 kg/m is not more than 2.5 ppm in the tension direction and not more than 10 ppm in the direction perpendicular to the tension direction.

摘要翻译： 公开了一种具有高尺寸稳定性的粘合膜，其可以适用于两层FPC。 具体地，公开了由绝缘层和布置在绝缘层的一侧或两侧上的粘合层构成的粘合片。 该粘合片的特征在于绝缘层在25℃下的储能弹性模量E'1与380℃下的储能弹性模量E'2之间的比率E'2 / E'1不大于 0.2，在100〜200℃下MD方向的热膨胀系数为5〜15ppm。其特征还在于，热处理后的粘合片的热膨胀系数在100〜250℃的变化 在拉伸方向下在380℃，30秒的拉伸下处理30秒，在拉伸方向垂直的方向不大于10ppm。

公开(公告)号：US20110073162A1

公开(公告)日：2011-03-31

申请号：US12993467

申请日：2009-05-15

申请人： Takashi Kikuchi ,  Toshiaki Sasaki

发明人： Takashi Kikuchi ,  Toshiaki Sasaki

IPC分类号： H01L31/052 ,  H01L31/18 ,  H01L31/0232

CPC分类号： H01L31/02168 ,  H01L31/03921 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/076 ,  H01L31/1804 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： Provided is a substrate for a thin-film photoelectric conversion device which makes it possible to produce the device having improved characteristics at low cost and high productivity. The substrate includes a transparent base member, with a transparent underlying layer and a transparent electrode layer successively stacked on one main surface of the transparent base member. The underlying layer includes transparent insulating fine particles and transparent binder, and the particles are dispersed to cover the one main surface with a coverage factor of particles—ranging from 30% or more to less than 80%. An antireflection layer is provided on the other main surface of the transparent base. The antireflection layer includes transparent insulating fine particles and transparent binder, and the particles are dispersed to cover the other main surface with a coverage factor greater than the underlying layer. The transparent electrode layer contains zinc oxide deposited by low-pressure CVD method.

摘要翻译： 本发明提供一种薄膜光电转换装置用基板，能够以低成本，高生产率制造具有改善特性的装置。 基板包括透明基底构件，透明基底层和依次层叠在透明基底构件的一个主表面上的透明电极层。 下层包括透明绝缘细颗粒和透明粘合剂，并且颗粒被分散以覆盖一个主表面，其颗粒的覆盖因子范围为30％以上至小于80％。 在透明基材的另一个主表面上设置防反射层。 抗反射层包括透明绝缘细颗粒和透明粘合剂，并且颗粒被分散以覆盖另一个主表面，覆盖因子大于下层。 透明电极层含有通过低压CVD法沉积的氧化锌。