公开(公告)号：US20060189099A1

公开(公告)日：2006-08-24

申请号：US11174710

申请日：2005-07-05

申请人： Szu Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.

摘要翻译： 提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。 使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。 在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。 两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。 这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。

公开(公告)号：US20060220244A1

公开(公告)日：2006-10-05

申请号：US11082298

申请日：2005-03-17

申请人： Szu Lu ,  Hsin-Hui Lee ,  Chung Wang ,  Mirng-Ji Lii

发明人： Szu Lu ,  Hsin-Hui Lee ,  Chung Wang ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2924/013

摘要： A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

摘要翻译： 半导体封装组件包括半导体衬底上的第一导电焊盘; 封装衬底上的第二导电焊盘; 物理耦合在所述第一导电焊盘和所述第二导电焊盘之间的突起，其中所述突起基本上是无铅或高含铅的; 所述凸块具有与所述第一导电焊盘的第一界面，所述第一界面具有第一线性尺寸; 所述凸块具有与所述第二导电焊盘的第二接口，所述第二接口具有第二线性尺寸; 并且其中所述第一线性尺寸和所述第二线性尺寸的比率在约0.7和约1.7之间。

公开(公告)号：US20070238220A1

公开(公告)日：2007-10-11

申请号：US11393050

申请日：2006-03-29

申请人： Mirng-Ji Lii ,  Szu Lu ,  Tjandra Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu Lu ,  Tjandra Karta ,  Chien-Hsiun Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。

公开(公告)号：US20060208352A1

公开(公告)日：2006-09-21

申请号：US11082675

申请日：2005-03-17

申请人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Lu

发明人： Hsin-Hui Lee ,  Mickey Ken ,  Chien-Hsiun Lee ,  Szu Lu

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/81 ,  H01L29/045 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

摘要翻译： 公开了一种用于更好地封装半导体器件的方法和系统。 在一个示例中，半导体器件封装包括封装衬底，至少一个具有取向<100>的裸片放置在衬底上，其中在封装衬底和裸片之间形成电连接，以及将裸片附接到衬底 其中底部填充圆角在其至少一侧上达到小于模具厚度的60％。

公开(公告)号：US20070246821A1

公开(公告)日：2007-10-25

申请号：US11408155

申请日：2006-04-20

申请人： Szu Lu ,  Clinton Chao ,  Tjandra Karta ,  Jerry Tzou ,  Kuo-Chin Chang

发明人： Szu Lu ,  Clinton Chao ,  Tjandra Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L23/055 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.

摘要翻译： 提供了具有减小的应力的半导体封装组件及其形成方法。 该方法包括提供包括基材的封装衬底，形成覆盖封装衬底的互连结构，将至少一个芯片附接到封装衬底的第一表面，使封装衬底从与第一表面相反的第二表面变薄，其中半导体 基本上去除了材料，并且在将封装衬底细化之后，将球栅阵列（BGA）球附着到在封装衬底的第二表面上暴露的深通孔。