公开(公告)号：US11923433B2

公开(公告)日：2024-03-05

申请号：US17195967

申请日：2021-03-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Liang Pan ,  Yungtzu Chen ,  Chung-Chieh Lee ,  Yung-Chang Hsu ,  Chia-Yang Hung ,  Po-Chuan Wang ,  Guan-Xuan Chen ,  Huan-Just Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02126 ,  H01L21/0217 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

公开(公告)号：US11769770B2

公开(公告)日：2023-09-26

申请号：US17313575

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lien Huang ,  Che-Ming Hsu ,  Ching-Feng Fu ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5222 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2221/1063

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

公开(公告)号：US11239083B2

公开(公告)日：2022-02-01

申请号：US16740878

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Jyun Wu ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  G03F7/09 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/32 ,  H01L21/30 ,  H01L21/3205 ,  H01L21/324

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

公开(公告)号：US11094545B2

公开(公告)日：2021-08-17

申请号：US16513483

申请日：2019-07-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Maxi Chang ,  Chih-Tang Peng ,  Chih-Yang Yeh ,  Ta-Wei Lin ,  Huan-Just Lin ,  Hui-Wen Lin ,  Jen-Sheng Yang ,  Pei-Ren Jeng ,  Jung-Hui Kao ,  Shih-Hao Lo ,  Yuan-Tien Tu

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

公开(公告)号：US20190333820A1

公开(公告)日：2019-10-31

申请号：US15966858

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yun-Min Chang ,  Chien-An Chen ,  Guan-Ren Wang ,  Peng Wang ,  Huang-Ming Chen ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L27/088

Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.

公开(公告)号：US20180019133A1

公开(公告)日：2018-01-18

申请号：US15717520

申请日：2017-09-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jin-Aun Ng ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang ,  Maxi Chang ,  Chih-Tang Peng ,  Chih-Yang Yeh ,  Ta-Wei Lin ,  Huan-Just Lin ,  Hui-Wen Lin ,  Jen-Sheng Yang ,  Pei-Ren Jeng ,  Jung-Hui Kao ,  Shih-Hao Lo ,  Yuan-Tien Tu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

公开(公告)号：US09741621B2

公开(公告)日：2017-08-22

申请号：US15430174

申请日：2017-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Feng Fu ,  De-Fang Chen ,  Yu-Chan Yen ,  Chia-Ying Lee ,  Chun-Hung Lee ,  Huan-Just Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78642

Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.

公开(公告)号：US09685332B2

公开(公告)日：2017-06-20

申请号：US14517252

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： De-Fang Chen ,  Huan-Just Lin ,  Chun-Hung Lee ,  Chao-Cheng Chen

IPC: H01L29/94 ,  H01L21/033

CPC classification number: H01L21/0337

Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.

公开(公告)号：US09570358B2

公开(公告)日：2017-02-14

申请号：US15230225

申请日：2016-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Feng Fu ,  De-Fang Chen ,  Yu-Chan Yen ,  Chia-Ying Lee ,  Chun-Hung Lee ,  Huan-Just Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/02 ,  H01L21/308

CPC classification number: H01L21/823487 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78642

Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.

Abstract translation: 一种方法包括将第一图案化工艺应用于第一光致抗蚀剂层以在牺牲层中形成第一开口，第二开口，第三开口和第四开口，对第二光致抗蚀剂层施加第二图案化工艺以形成第五开口 ，第六开口，第七开口和第八开口，其中由第一和第二图案化工艺形成的两个相邻开口之间的距离基本相等，对第三光致抗蚀剂层施加第三图案化工艺以形成 第九开口，第十开口，第十一开口和第十二开口，其中由第二和第三图案化工艺形成的两个相邻开口之间的距离基本相等，并且基于开口形成多个纳米线 。

公开(公告)号：US20150348848A1

公开(公告)日：2015-12-03

申请号：US14289167

申请日：2014-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Feng Fu ,  De-Fang Chen ,  Yu-Chan Yen ,  Chia-Ying Lee ,  Chun-Hung Lee ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/311 ,  H01L23/528 ,  H01L21/306 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823487 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/823412 ,  H01L21/823418 ,  H01L23/528 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底上形成图案保留层。 半导体衬底具有主表面。 执行第一自对准多图案化处理以对图案保留层进行图案化。 图案保留层的剩余部分包括沿与半导体基板的主表面平行的第一方向延伸的图案预留条。 执行第二自对准多图案化工艺以在与半导体衬底的主表面平行的第二方向上对图案保留层进行图案化。 图案保留层的其余部分包括图案特征。 图案化特征被用作蚀刻掩模以通过蚀刻半导体衬底形成半导体纳米线。