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公开(公告)号：US12087636B2
公开(公告)日：2024-09-10
申请号：US17804927
申请日：2022-06-01
发明人： Kuo-Cheng Ching , Zhi-Chang Lin , Shi Ning Ju , Chih-Hao Wang , Kuan-Ting Pan
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823431 , H01L21/823418 , H01L21/823481 , H01L27/0886
摘要： The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.
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公开(公告)号：US12034062B2
公开(公告)日：2024-07-09
申请号：US17980656
申请日：2022-11-04
发明人： Kuo-Cheng Ching , Zhi-Chang Lin , Kuan-Ting Pan , Chih-Hao Wang , Shi-Ning Ju
IPC分类号： H01L29/66 , H01L21/02 , H01L21/033 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/02507 , H01L21/0337 , H01L21/76832 , H01L21/76834 , H01L21/76876 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L27/0886 , H01L29/66545 , H01L29/785
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.
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公开(公告)号：US11824058B2
公开(公告)日：2023-11-21
申请号：US18082333
申请日：2022-12-15
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L21/308 , H01L21/8238 , H01L21/28 , H01L29/66 , H01L29/78 , H01L29/49 , H01L29/51
CPC分类号： H01L27/0924 , H01L21/28088 , H01L21/3086 , H01L21/823821 , H01L21/823864 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/785
摘要： Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.
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公开(公告)号：US11410887B2
公开(公告)日：2022-08-09
申请号：US16717367
申请日：2019-12-17
发明人： Kuo-Cheng Ching , Ying-Keung Leung
IPC分类号： H01L21/8232 , H01L21/8238 , H01L21/84 , H01L21/02 , H01L27/12 , H01L27/092 , H01L29/66
摘要： The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
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公开(公告)号：US11367659B2
公开(公告)日：2022-06-21
申请号：US16726518
申请日：2019-12-24
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/161 , H01L29/16 , H01L27/088 , H01L29/06 , H01L29/78
摘要： A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
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公开(公告)号：US11171238B2
公开(公告)日：2021-11-09
申请号：US16046541
申请日：2018-07-26
发明人： Kuo-Cheng Ching , Ka-Hing Fung , Chih-Sheng Chang , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/06 , H01L29/66 , H01L29/49 , H01L29/51 , H01L21/762 , H01L21/02
摘要： Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.
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公开(公告)号：US11004847B2
公开(公告)日：2021-05-11
申请号：US16684929
申请日：2019-11-15
发明人： Kuo-Cheng Ching , Ting-Hung Hsu
IPC分类号： H01L27/092 , H01L29/66 , H01L29/775 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/10 , H01L29/78 , H01L29/51 , H01L29/06
摘要： An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
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公开(公告)号：US20200058770A1
公开(公告)日：2020-02-20
申请号：US16665289
申请日：2019-10-28
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/8234
摘要： A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region.
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公开(公告)号：US20200006156A1
公开(公告)日：2020-01-02
申请号：US16564249
申请日：2019-09-09
发明人： Kuo-Cheng Ching , Ka-Hing Fung , Zhiqiang Wu
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/165 , H01L29/10 , H01L21/02 , H01L21/3105 , H01L21/762
摘要： Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.
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公开(公告)号：US10522416B2
公开(公告)日：2019-12-31
申请号：US15955317
申请日：2018-04-17
发明人： Kuo-Cheng Ching , Ying-Keung Leung
IPC分类号： H01L21/8232 , H01L21/8238 , H01L21/84 , H01L21/02 , H01L27/12 , H01L27/092 , H01L29/66
摘要： The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
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