公开(公告)号：US20150206963A1

公开(公告)日：2015-07-23

申请号：US14158572

申请日：2014-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： WEI-SHUO HO ,  TSUNG-YU CHIANG ,  KUANG-HSIN CHEN

IPC: H01L29/78 ,  H01L21/3215 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/3215 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer. A thickness of a first portion of the barrier layer at the sidewall of the metal gate is substantially thinner than a thickness of the barrier layer at the bottom of the metal gate. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate trench in an ILD, forming a barrier layer in a bottom and a sidewall of the metal gate trench, removing a first portion of the barrier layer at the sidewall of the metal gate trench, and forming a work function metal layer conforming to the barrier layer.

Abstract translation: 本公开提供一种半导体结构，其包括具有第一表面的半导体层和在半导体层的第一表面上限定金属栅极的层间电介质（ILD）。 金属栅极包括高k电介质层，阻挡层和功函数金属层。 在金属栅极的侧壁处的阻挡层的第一部分的厚度基本上比金属栅极底部的阻挡层的厚度薄。 本公开提供了一种用于制造半导体结构的方法。 该方法包括在ILD中形成金属栅极沟槽，在金属栅极沟槽的底部和侧壁中形成阻挡层，在金属栅极沟槽的侧壁处去除势垒层的第一部分，并形成功函数 符合阻挡层的金属层。

公开(公告)号：US20170125301A1

公开(公告)日：2017-05-04

申请号：US15358061

申请日：2016-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： WEI-SHUO HO ,  TSUNG-YU CHIANG ,  KUANG-HSIN CHEN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/283 ,  H01L21/306 ,  H01L21/311 ,  H01L29/49 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/518 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

公开(公告)号：US20160056262A1

公开(公告)日：2016-02-25

申请号：US14463953

申请日：2014-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： WEI-SHUO HO ,  CHANG-YIN CHEN ,  CHAI-WEI CHANG ,  TSUNG-YU CHIANG

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/283 ,  H01L21/02 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L29/66545 ,  H01L21/47635 ,  H01L21/823468 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.

Abstract translation: 本公开的一些实施例提供了半导体器件，其包括半导体衬底，金属栅极，其包括靠近半导体衬底的金属层。 电介质层围绕金属栅极。 电介质层包括面向半导体衬底的第一表面和与第一表面相对的第二表面。 侧壁间隔件以更大的纵向高度包围金属层。 侧壁间隔件设置在金属层和电介质层之间。 金属栅极上的蚀刻停止层包括与介电层的第二表面基本上共面的表面。 蚀刻停止层比电介质层具有更高的蚀刻剂耐性。 蚀刻停止层的一部分在侧壁间隔物上方。