公开(公告)号：US11764174B2

公开(公告)日：2023-09-19

申请号：US17534419

申请日：2021-11-23

申请人： United Microelectronics Corp.

发明人： Chun-Chi Huang ,  Hui-Lung Chou ,  Chuang-Han Hsieh ,  Yung-Feng Lin ,  Shin-Chi Chen

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L24/02 ,  H01L23/528 ,  H01L24/05 ,  H01L23/53295 ,  H01L2224/0219 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/05557

摘要： A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

公开(公告)号：US20170358546A1

公开(公告)日：2017-12-14

申请号：US15617425

申请日：2017-06-08

申请人： WISOL CO., LTD.

发明人： Young Seok SHIM ,  Hyung Ju KIM ,  Joo Hun PARK ,  Chang Dug KIM

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/02175 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02206 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16112 ,  H01L2224/81205 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/3512

摘要： A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

公开(公告)号：US09812414B1

公开(公告)日：2017-11-07

申请号：US15186100

申请日：2016-06-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po Chun Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L24/02 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/06 ,  H01L2924/00014 ,  H01L2924/014

摘要： A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first insulation layer; a buffering member embedded into the first insulation layer; a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member.

公开(公告)号：US20170186733A1

公开(公告)日：2017-06-29

申请号：US15457744

申请日：2017-03-13

申请人： IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

发明人： Vikas Dubey ,  Ingrid De Wolf ,  Eric Beyne

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/528 ,  H01L24/02 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/02185 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/80121 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80203 ,  H01L2224/80894 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81894 ,  H01L2224/81907 ,  H01L2224/83143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

公开(公告)号：US20170086304A1

公开(公告)日：2017-03-23

申请号：US14859026

申请日：2015-09-18

申请人： Delaware Capital Formation, Inc.

发明人： Mark Hahn

IPC分类号： H05K3/10 ,  B23K26/0622 ,  B23K9/09 ,  B23K26/21 ,  H05K1/18 ,  B23K9/167

CPC分类号： H05K3/103 ,  B23K9/0043 ,  B23K9/091 ,  B23K9/092 ,  B23K9/167 ,  B23K9/23 ,  B23K26/0622 ,  B23K26/21 ,  B23K26/22 ,  B23K26/32 ,  B23K2101/38 ,  B23K2103/00 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/42 ,  H01L24/44 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02163 ,  H01L2224/02185 ,  H01L2224/04042 ,  H01L2224/45147 ,  H01L2224/45639 ,  H01L2224/48476 ,  H01L2224/80007 ,  H01L2224/80009 ,  H01L2224/8019 ,  H01L2224/8034 ,  H01L2924/00014 ,  H05K1/18 ,  H05K3/328 ,  H05K2201/10242 ,  H05K2201/10265 ,  H05K2201/10287 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

公开(公告)号：US20240203919A1

公开(公告)日：2024-06-20

申请号：US18082285

申请日：2022-12-15

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： JOHN CARLO CRUZ MOLINA ,  RAFAEL JOSE LIZARES GUEVARA

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L21/78 ,  H01L23/31 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02175 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/13551 ,  H01L2224/136

摘要： An electronic device that includes a semiconductor substrate and a conductive structure disposed over the semiconductor substrate. An insulator layer overlies the semiconductor substrate and includes a tapered opening that overlies a portion of the conductive structure. A flanged conductive column that includes a base portion is disposed in the tapered opening and is coupled to the portion of the conductive structure. The flanged conductive column further includes a flanged portion that is configured to be exposed to provide a conductive contact to the electronic device.

公开(公告)号：US11855014B2

公开(公告)日：2023-12-26

申请号：US17120825

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Ming-Che Ho ,  Hung-Jui Kuo ,  Yi-Wen Wu ,  Tzung-Hui Lee

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538

CPC分类号： H01L24/02 ,  H01L22/14 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/02185 ,  H01L2224/02315 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/2747 ,  H01L2224/27462 ,  H01L2224/29018 ,  H01L2224/29036 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/0215 ,  H01L2924/06 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/27

摘要： A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

公开(公告)号：US11735559B2

公开(公告)日：2023-08-22

申请号：US17871616

申请日：2022-07-22

申请人： SK hynix Inc.

发明人： Chan Sun Lee

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L25/065

CPC分类号： H01L24/48 ,  H01L21/78 ,  H01L24/06 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0219 ,  H01L2224/02185 ,  H01L2224/04042 ,  H01L2224/06132 ,  H01L2224/06515 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48992 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/07025

摘要： A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

公开(公告)号：US10083924B2

公开(公告)日：2018-09-25

申请号：US14891319

申请日：2014-11-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kazuyoshi Maekawa ,  Yuichi Kawano

IPC分类号： H01L23/12 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L24/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/035 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05664 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48664 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/01008

摘要： A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

公开(公告)号：US09583425B2

公开(公告)日：2017-02-28

申请号：US13929978

申请日：2013-06-28

申请人： Maxim Integrated Products, Inc.

发明人： Yong Li Xu ,  Tiao Zhou ,  Xiansong Chen ,  Kaysar M. Rahim ,  Viren Khandekar ,  Yi-Sheng Anthony Sun ,  Arkadii V. Samoilov

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/13013 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/29013 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/3316 ,  H01L2224/81192 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83815 ,  H01L2924/351 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

摘要： A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

摘要翻译： 晶片级封装包括晶片，用于将晶片连接到电路的晶片设置的引线和设置在引线上的芯。 在一些实施例中，设置晶片的引线是铜柱，并且芯被镀在铜柱上。 在一些实施方案中，芯是聚合物丝网电镀到引线上。 在一些实施例中，芯从引线延伸至少约35微米（35微米）和50微米（50μm）。 在一些实施例中，芯覆盖在铅的表面积的至少约三分之一（1/3）和一半（1/2）之间。 在一些实施例中，芯包括从引线延伸的螺柱形状。 在一些实施例中，芯垂直延伸穿过导线。 在一些实施例中，芯沿着引线纵向延伸。 此外，芯的一部分可以从纵向芯垂直延伸。