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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160197016A1

    公开(公告)日：2016-07-07

    申请号：US15070802

    申请日：2016-03-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Shuo HO ,  Tsung-Yu CHIANG ,  Chia-Chun LIAO ,  Kuang-Hsin CHEN

    IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/28

    CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The method includes forming a gate dielectric layer in the first opening and the second opening. The method includes forming a film over the gate dielectric layer. The method includes forming a first work function metal layer in the first opening. The method includes depositing a second work function metal layer in the first opening and the second opening and in direct contact with the first work function metal layer in the first opening and the film in the second opening. A first deposition rate of the second work function metal layer over the first work function metal layer is greater than a second deposition rate of the second work function metal layer over the film.

    Abstract translation: 提供一种形成半导体器件的方法。 该方法包括提供其上形成有绝缘层的半导体衬底。 该方法包括在第一开口和第二开口中形成栅介质层。 该方法包括在栅介电层上形成膜。 该方法包括在第一开口中形成第一功函数金属层。 该方法包括在第一开口和第二开口中沉积第二功函数金属层，并与第一开口中的第一功函数金属层和第二开口中的膜直接接触。 第一功函数金属层上的第二功函数金属层的第一沉积速率大于膜上的第二功函数金属层的第二沉积速率。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160064567A1

    公开(公告)日：2016-03-03

    申请号：US14475132

    申请日：2014-09-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Shuo HO ,  Chia-Ming CHANG ,  Tsung-Yu CHIANG ,  Kuang-Hsin CHEN ,  Bor-Zen TIEN

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51

    CPC classification number: H01L29/7851 ,  H01L21/0223 ,  H01L29/511 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6681

    Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

    Abstract translation: 本公开的实施例大体上涉及半导体器件及其制造方法，半导体器件包括半导体衬底和设置在半导体器件的沟道区域上的栅极堆叠，栅极堆叠包括氧化层，栅极电介质 和栅电极，所述氧化层至少覆盖半导体器件的沟道区域的一部分，并且可以用作屏障，以在去除虚拟栅极期间防止对诸如源极和漏极区域的下伏特征的损坏 最后一道门。

    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    半导体器件结构及其形成方法

    公开(公告)号：US20160126309A1

    公开(公告)日：2016-05-05

    申请号：US14530060

    申请日：2014-10-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

    Inventor： An-Lun LO ,  Wei-Shuo HO ,  Tzong-Sheng CHANG ,  Chrong-Jung LIN ,  Ya-Chin KING

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.

    Abstract translation: 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括位于半导体衬底上的第一栅极堆叠。 半导体器件结构包括第一掺杂结构和第二掺杂结构，其位于第一栅极堆叠的两个相对侧并且嵌入在半导体衬底中。 半导体器件结构包括位于半导体衬底上并与第二掺杂结构相邻的第二栅极堆叠。 半导体器件结构包括位于半导体衬底上的第三栅极堆叠。 半导体器件结构包括嵌入在半导体衬底中以及在第二栅极堆叠和第三栅极叠层之间的隔离结构。 隔离结构比第二掺杂结构更宽和更薄，并且隔离结构由外延材料制成。

    MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE
    8.
    发明申请
    MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE 有权
    改进的自对准接触过程和半导体器件

    公开(公告)号：US20160211344A1

    公开(公告)日：2016-07-21

    申请号：US15083383

    申请日：2016-03-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tsung-Yu CHIANG ,  Wei-Shuo HO ,  Kuang-Hsin CHEN

    IPC: H01L29/49

    CPC classification number: H01L29/4966 ,  H01L21/31053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32138 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545

    Abstract: A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region. The high-k dielectric layer is over the substrate. The work function metal layer is over the high-k dielectric layer. The metal gate is over the work function metal layer. The two spacers sandwich the work function metal layer and the metal gate. The metal compound is over inner walls of the two spacers and over the top surface of the work function metal layer and the metal gate. The insulator covers the metal compound. The doped region is in the substrate. The contact pad is electrically connected to the metal gate.

    Abstract translation: 半导体器件包括晶体管和衬底上的接触焊盘。 晶体管包括高k电介质层，功函数金属层，金属栅极，两个间隔物，金属化合物，绝缘体和掺杂区域。 高k电介质层在衬底上。 功函数金属层位于高k电介质层之上。 金属门在工作功能金属层上方。 两个间隔物夹着功函数金属层和金属栅。 金属化合物在两个间隔物的内壁上方，并在功函数金属层和金属栅极的顶表面上方。 绝缘体覆盖金属化合物。 掺杂区域在衬底中。 接触垫电连接到金属门。

    MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE
    9.
    发明申请
    MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE 有权
    改进的自对准接触过程和半导体器件

    公开(公告)号：US20150228746A1

    公开(公告)日：2015-08-13

    申请号：US14175523

    申请日：2014-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Yu CHIANG ,  Wei-Shuo HO ,  Kuang-Hsin CHEN

    IPC: H01L29/49 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/4966 ,  H01L21/31053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32138 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545

    Abstract: Methods of modifying a self-aligned contact process in a semiconductor fabrication and a semiconductor device are provided. A method includes forming a transistor over a substrate, including depositing a high-k dielectric layer over the substrate; depositing a work function metal layer over the high-k dielectric layer; forming a metal gate over the work function metal layer; forming two spacers sandwiching the work function metal layer and the metal gate; and forming a doped region in the substrate; etching the work function metal layer and the metal gate to leave a metal residue over inner walls of the two spacers exposing the work function metal layer and the metal gate; modifying the metal residue and the exposed work function metal layer and metal gate to form a metal compound; depositing an insulator covering the metal compound; and forming contact pads respectively electrically connected to the metal gate and the doped region.

    Abstract translation: 提供了在半导体制造和半导体器件中修改自对准接触工艺的方法。 一种方法包括在衬底上形成晶体管，包括在衬底上沉积高k电介质层; 在高k电介质层上沉积功函数金属层; 在工作功能金属层上形成金属栅极; 形成夹着功能金属层和金属栅极的两个间隔物; 以及在所述衬底中形成掺杂区域; 蚀刻功函数金属层和金属栅极，在两个间隔物的内壁上留下金属残留物，暴露功函数金属层和金属栅; 改性金属残渣和暴露的功函数金属层和金属栅极，形成金属化合物; 沉积覆盖金属化合物的绝缘体; 以及形成分别电连接到金属栅极和掺杂区域的接触焊盘。

    SEMICONDUCTOR DEVICE WITH GATE STACKS AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE WITH GATE STACKS AND METHOD OF MANUFACTURING THE SAME 有权
    具有盖板的半导体器件及其制造方法

    公开(公告)号：US20150221743A1

    公开(公告)日：2015-08-06

    申请号：US14174379

    申请日：2014-02-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Wei-Shuo HO ,  Tsung-Yu CHIANG ,  Chia-Chun LIAO ,  Kuang-Hsin CHEN

    IPC: H01L29/49 ,  H01L21/28 ,  H01L27/088

    CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate stack. The first gate stack includes a gate dielectric layer, a first work function metal layer and a second work function metal layer directly on the first work function metal layer. The second work function metal layer and the first work function metal layer have the same metal element. The semiconductor device also includes a second gate stack. The second gate stack includes a gate dielectric layer, a barrier layer and a second work function metal layer. The second work function metal layer and the barrier layer do not have the same metal element. A first thickness of the second work function metal layer of the first gate stack is larger than a second thickness of the second work function metal layer of the second gate stack.

    Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底和第一栅极堆叠。 第一栅极堆叠包括直接在第一功函数金属层上的栅介电层，第一功函数金属层和第二功函数金属层。 第二功函数金属层和第一功函数金属层具有相同的金属元素。 半导体器件还包括第二栅极堆叠。 第二栅极堆叠包括栅极介电层，阻挡层和第二功函数金属层。 第二功函数金属层和阻挡层不具有相同的金属元素。 第一栅极堆叠的第二功函数金属层的第一厚度大于第二栅极堆叠的第二功函数金属层的第二厚度。

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