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公开(公告)号：US20230314719A1
公开(公告)日：2023-10-05
申请号：US18331184
申请日：2023-06-08
发明人： Chan-Hong Chern , Chih-Chang Lin , Chewn-Pu Jou , Chih-Tsung Shih , Feng-Wei Kuo , Lan-Chou Cho , Min-Hsiang Hsu , Weiwei Song
CPC分类号： G02B6/305 , G02B6/124 , G02B6/30 , G02B6/29317
摘要： An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
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公开(公告)号：US11769845B2
公开(公告)日：2023-09-26
申请号：US17838386
申请日：2022-06-13
发明人： Chan-Hong Chern , Weiwei Song , Chih-Chang Lin , Lan-Chou Cho , Min-Hsiang Hsu
IPC分类号： H01L31/0352 , H01L31/18 , H01L31/105 , G01J1/42
CPC分类号： H01L31/035254 , G01J1/42 , H01L31/035281 , H01L31/105 , H01L31/1804
摘要： The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, a first doped region having a first conductivity type at a first side of the photosensitive member, wherein the first doped region is in the silicon layer, and a second doped region having a second conductivity type different from the first conductivity type at a second side of the photosensitive member opposite to the first side, wherein the second doped region is in the silicon layer, and the first doped region is apart from the second doped region, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material.
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公开(公告)号：US20220357518A1
公开(公告)日：2022-11-10
申请号：US17874228
申请日：2022-07-26
发明人： Chan-Hong Chern , Chih-Chang Lin , Chewn-Pu Jou , Chih-Tsung Shih , Feng-Wei Kuo , Lan-Chou Cho , Min-Hsiang Hsu , Weiwei Song
摘要： An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
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公开(公告)号：US20220269006A1
公开(公告)日：2022-08-25
申请号：US17180864
申请日：2021-02-22
发明人： Chan-Hong Chern , Chih-Chang Lin , Chewn-Pu Jou , Chih-Tsung Shih , Feng-Wei Kuo , Lan-Chou Cho , Min-Hsiang Hsu , Weiwei Song
摘要： An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
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公开(公告)号：US10401889B2
公开(公告)日：2019-09-03
申请号：US14989113
申请日：2016-01-06
摘要： A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.
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公开(公告)号：US10367491B2
公开(公告)日：2019-07-30
申请号：US16005435
申请日：2018-06-11
IPC分类号： H03L7/00 , H03L7/06 , H03K3/42 , G06G7/16 , H03L7/08 , H03K5/13 , H03K5/134 , H03K5/14 , H03K5/00
摘要： A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
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公开(公告)号：US10298237B2
公开(公告)日：2019-05-21
申请号：US15870356
申请日：2018-01-12
IPC分类号： H03K19/0185
摘要： A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
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公开(公告)号：US09871521B2
公开(公告)日：2018-01-16
申请号：US15049919
申请日：2016-02-22
IPC分类号： H03K19/0185
CPC分类号： H03K19/018507 , H03K19/0185 , H03K19/018521
摘要： A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.
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公开(公告)号：US09831860B2
公开(公告)日：2017-11-28
申请号：US15003330
申请日：2016-01-21
发明人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
CPC分类号： H03K5/1515
摘要： A clock generation circuit includes a two-phase non-overlapping clock generation circuit, an inverter, and a delay circuit. The two-phase non-overlapping clock generation circuit is configured to generate a first phase clock signal and a second phase clock signal based on a non-inverted clock signal and an inverted clock signal. The first phase clock signal and the second phase clock signal correspond to a same logical value during a first duration and a second duration within a clock cycle. The inverter is configured to generate the inverted clock signal based on an input clock signal. The delay circuit is configured to generate the non-inverted clock signal based on the input clock signal. The delay circuit has a predetermined delay sufficient to cause a difference between the first duration and the second duration to be less than a predetermined tolerance.
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公开(公告)号：US09601489B2
公开(公告)日：2017-03-21
申请号：US14959786
申请日：2015-12-04
发明人： Chan-Hong Chern , Chih-Chang Lin , Julie Tran , Jacklyn Chang
IPC分类号： H01L27/02 , H01L27/092 , H01L21/321 , H01L29/423 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/3212 , H01L21/82385 , H01L27/0207 , H01L27/092 , H01L29/42364 , H01L29/42376
摘要： The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
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